Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'

[u-boot] / arch / arm / cpu / armv7 / omap3 / board.c

diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 9cee1d9b490692d02129d98470ba7b57b8e61ce2..c6d9a425a592d7fae469fa0acc0b733fe99836c6 100644 (file)
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -50,7 +50,9 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Declarations */
 extern omap3_sysinfo sysinfo;
 static void omap3_setup_aux_cr(void);
+#ifndef CONFIG_SYS_L2CACHE_OFF
 static void omap3_invalidate_l2_cache_secure(void);
+#endif
 
 static const struct gpio_bank gpio_bank_34xx[6] = {
        { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
@@ -96,11 +98,11 @@ int board_mmc_init(bd_t *bis)
 {
        switch (spl_boot_device()) {
        case BOOT_DEVICE_MMC1:
-               omap_mmc_init(0, 0, 0);
+               omap_mmc_init(0, 0, 0, -1, -1);
                break;
        case BOOT_DEVICE_MMC2:
        case BOOT_DEVICE_MMC2_2:
-               omap_mmc_init(1, 0, 0);
+               omap_mmc_init(1, 0, 0, -1, -1);
                break;
        }
        return 0;
@@ -108,7 +110,7 @@ int board_mmc_init(bd_t *bis)
 
 void spl_board_init(void)
 {
-#ifdef CONFIG_SPL_NAND_SUPPORT
+#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
        gpmc_init();
 #endif
 #ifdef CONFIG_SPL_I2C_SUPPORT
@@ -410,19 +412,6 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
        }
 }
 
-static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
-{
-       u32 acr;
-
-       /* Read ACR */
-       asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
-       acr &= ~clear_bits;
-       acr |= set_bits;
-
-       /* Write ACR - affects non-secure banked bits */
-       asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
-}
-
 static void omap3_setup_aux_cr(void)
 {
        /* Workaround for Cortex-A8 errata: #454179 #430973
@@ -436,6 +425,19 @@ static void omap3_setup_aux_cr(void)
 }
 
 #ifndef CONFIG_SYS_L2CACHE_OFF
+static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
+{
+       u32 acr;
+
+       /* Read ACR */
+       asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
+       acr &= ~clear_bits;
+       acr |= set_bits;
+
+       /* Write ACR - affects non-secure banked bits */
+       asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
+}
+
 /* Invalidate the entire L2 cache from secure mode */
 static void omap3_invalidate_l2_cache_secure(void)
 {
@@ -476,7 +478,7 @@ void omap3_outer_cache_disable(void)
         */
        omap3_update_aux_cr(0, 0x2);
 }
-#endif
+#endif /* !CONFIG_SYS_L2CACHE_OFF */
 
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
@@ -484,4 +486,4 @@ void enable_caches(void)
        /* Enable D-cache. I-cache is already enabled in start.S */
        dcache_enable();
 }
-#endif
+#endif /* !CONFIG_SYS_DCACHE_OFF */