mmc:sdhci:fix: Change default interrupts enabled at SDHCI initialization

[u-boot] / arch / arm / cpu / armv7 / omap4 / clocks.c

diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c
index 0886f92431ad87ace2cd2823196580b8cd3693e7..12c58033d2600371c78ab8ae8de40216c1e83c55 100644 (file)
--- a/arch/arm/cpu/armv7/omap4/clocks.c
+++ b/arch/arm/cpu/armv7/omap4/clocks.c
@@ -44,9 +44,7 @@
  */
 #define printf(fmt, args...)
 #define puts(s)
-#endif
-
-#define abs(x) (((x) < 0) ? ((x)*-1) : (x))
+#endif /* !CONFIG_SPL_BUILD */
 
 struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100;
 
@@ -67,15 +65,15 @@ const u32 sys_clk_array[8] = {
  * Please use this tool for creating the table for any new frequency.
  */
 
-/* dpll locked at 1840 MHz MPU clk at 920 MHz(OPP Turbo 4460) - DCC OFF */
-static const struct dpll_params mpu_dpll_params_1840mhz[NUM_SYS_CLKS] = {
-       {230, 2, 1, -1, -1, -1, -1, -1},        /* 12 MHz   */
-       {920, 12, 1, -1, -1, -1, -1, -1},       /* 13 MHz   */
-       {219, 3, 1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
-       {575, 11, 1, -1, -1, -1, -1, -1},       /* 19.2 MHz */
-       {460, 12, 1, -1, -1, -1, -1, -1},       /* 26 MHz   */
-       {920, 26, 1, -1, -1, -1, -1, -1},       /* 27 MHz   */
-       {575, 23, 1, -1, -1, -1, -1, -1}        /* 38.4 MHz */
+/* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */
+static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
+       {175, 2, 1, -1, -1, -1, -1, -1},        /* 12 MHz   */
+       {700, 12, 1, -1, -1, -1, -1, -1},       /* 13 MHz   */
+       {125, 2, 1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
+       {401, 10, 1, -1, -1, -1, -1, -1},       /* 19.2 MHz */
+       {350, 12, 1, -1, -1, -1, -1, -1},       /* 26 MHz   */
+       {700, 26, 1, -1, -1, -1, -1, -1},       /* 27 MHz   */
+       {638, 34, 1, -1, -1, -1, -1, -1}        /* 38.4 MHz */
 };
 
 /* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
@@ -148,7 +146,7 @@ static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
        {727, 14, -1, -1, 4, 7, -1, -1},        /* 19.2 MHz */
        {931, 25, -1, -1, 4, 7, -1, -1},        /* 26 MHz   */
        {931, 26, -1, -1, 4, 7, -1, -1},        /* 27 MHz   */
-       {412, 16, -1, -1, 4, 7, -1, -1}         /* 38.4 MHz */
+       {291, 11, -1, -1, 4, 7, -1, -1}         /* 38.4 MHz */
 };
 
 /* ABE M & N values with sys_clk as source */
@@ -217,7 +215,7 @@ const struct dpll_params *get_mpu_dpll_params(void)
        else if (omap_rev < OMAP4460_ES1_0)
                return &mpu_dpll_params_1600mhz[sysclk_ind];
        else
-               return &mpu_dpll_params_1840mhz[sysclk_ind];
+               return &mpu_dpll_params_1400mhz[sysclk_ind];
 }
 
 const struct dpll_params *get_core_dpll_params(void)
@@ -275,47 +273,70 @@ void scale_vcores(void)
 {
        u32 volt, omap_rev;
 
-       setup_sri2c();
+       omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
 
        omap_rev = omap_revision();
-       /* TPS - supplies vdd_mpu on 4460 */
-       if (omap_rev >= OMAP4460_ES1_0) {
-               volt = 1313;
-               do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt);
-       }
 
        /*
-        * VCORE 1
-        *
-        * 4430 : supplies vdd_mpu
-        * Setting a high voltage for Nitro mode as smart reflex is not enabled.
-        * We use the maximum possible value in the AVS range because the next
-        * higher voltage in the discrete range (code >= 0b111010) is way too
-        * high
-        *
-        * 4460 : supplies vdd_core
+        * Scale Voltage rails:
+        * 1. VDD_CORE
+        * 3. VDD_MPU
+        * 3. VDD_IVA
         */
        if (omap_rev < OMAP4460_ES1_0) {
+               /*
+                * OMAP4430:
+                * VDD_CORE = TWL6030 VCORE3
+                * VDD_MPU = TWL6030 VCORE1
+                * VDD_IVA = TWL6030 VCORE2
+                */
+               volt = 1200;
+               do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
+
+               /*
+                * note on VDD_MPU:
+                * Setting a high voltage for Nitro mode as smart reflex is not
+                * enabled. We use the maximum possible value in the AVS range
+                * because the next higher voltage in the discrete range
+                * (code >= 0b111010) is way too high.
+                */
                volt = 1325;
                do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
+               volt = 1200;
+               do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
+
        } else {
+               /*
+                * OMAP4460:
+                * VDD_CORE = TWL6030 VCORE1
+                * VDD_MPU = TPS62361
+                * VDD_IVA = TWL6030 VCORE2
+                */
                volt = 1200;
                do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
+               /* TPS62361 */
+               volt = 1203;
+               do_scale_tps62361(TPS62361_VSEL0_GPIO,
+                                 TPS62361_REG_ADDR_SET1, volt);
+               /* VCORE 2 - supplies vdd_iva */
+               volt = 1200;
+               do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
        }
+}
 
-       /* VCORE 2 - supplies vdd_iva */
-       volt = 1200;
-       do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
+u32 get_offset_code(u32 offset)
+{
+       u32 offset_code, step = 12660; /* 12.66 mV represented in uV */
 
-       /*
-        * VCORE 3
-        * 4430 : supplies vdd_core
-        * 4460 : not connected
-        */
-       if (omap_rev < OMAP4460_ES1_0) {
-               volt = 1200;
-               do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
-       }
+       if (omap_revision() == OMAP4430_ES1_0)
+               offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
+       else
+               offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
+
+       offset_code = (offset + step - 1) / step;
+
+       /* The code starts at 1 not 0 */
+       return ++offset_code;
 }
 
 /*
@@ -333,6 +354,7 @@ void enable_basic_clocks(void)
        };
 
        u32 *const clk_modules_hw_auto_essential[] = {
+               &prcm->cm_l3_2_gpmc_clkctrl,
                &prcm->cm_memif_emif_1_clkctrl,
                &prcm->cm_memif_emif_2_clkctrl,
                &prcm->cm_l4cfg_l4_cfg_clkctrl,
@@ -388,6 +410,9 @@ void enable_basic_uboot_clocks(void)
        u32 *const clk_modules_hw_auto_essential[] = {
                &prcm->cm_l3init_hsusbotg_clkctrl,
                &prcm->cm_l3init_usbphy_clkctrl,
+               &prcm->cm_l3init_usbphy_clkctrl,
+               &prcm->cm_clksel_usb_60mhz,
+               &prcm->cm_l3init_hsusbtll_clkctrl,
                0
        };
 
@@ -397,6 +422,7 @@ void enable_basic_uboot_clocks(void)
                &prcm->cm_l4per_i2c2_clkctrl,
                &prcm->cm_l4per_i2c3_clkctrl,
                &prcm->cm_l4per_i2c4_clkctrl,
+               &prcm->cm_l3init_hsusbhost_clkctrl,
                0
        };
 
@@ -427,16 +453,10 @@ void enable_non_essential_clocks(void)
        };
 
        u32 *const clk_modules_hw_auto_non_essential[] = {
-               &prcm->cm_mpu_m3_mpu_m3_clkctrl,
-               &prcm->cm_ivahd_ivahd_clkctrl,
-               &prcm->cm_ivahd_sl2_clkctrl,
-               &prcm->cm_dsp_dsp_clkctrl,
-               &prcm->cm_l3_2_gpmc_clkctrl,
                &prcm->cm_l3instr_l3_3_clkctrl,
                &prcm->cm_l3instr_l3_instr_clkctrl,
                &prcm->cm_l3instr_intrconn_wp1_clkctrl,
                &prcm->cm_l3init_hsi_clkctrl,
-               &prcm->cm_l3init_hsusbtll_clkctrl,
                0
        };
 
@@ -476,8 +496,6 @@ void enable_non_essential_clocks(void)
                &prcm->cm_cam_fdif_clkctrl,
                &prcm->cm_dss_dss_clkctrl,
                &prcm->cm_sgx_sgx_clkctrl,
-               &prcm->cm_l3init_hsusbhost_clkctrl,
-               &prcm->cm_l3init_fsusb_clkctrl,
                0
        };