arm: ls102xa: workaround for cache coherency problem

[u-boot] / arch / arm / cpu / armv7 / omap4 / hw_data.c

diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c
index 1b2f439241d81cb83b665afb2ed6adbe9f43b6b3..029533c851831d0347d338353d7d2a7e3e29d98e 100644 (file)
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -172,6 +172,20 @@ struct dplls omap4430_dplls_es1 = {
        .ddr = NULL
 };
 
+struct dplls omap4430_dplls_es20 = {
+       .mpu = mpu_dpll_params_1200mhz,
+       .core = core_dpll_params_es2_1600mhz_ddr200mhz,
+       .per = per_dpll_params_1536mhz,
+       .iva = iva_dpll_params_1862mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+       .abe = abe_dpll_params_sysclk_196608khz,
+#else
+       .abe = &abe_dpll_params_32k_196608khz,
+#endif
+       .usb = usb_dpll_params_1920mhz,
+       .ddr = NULL
+};
+
 struct dplls omap4430_dplls = {
        .mpu = mpu_dpll_params_1200mhz,
        .core = core_dpll_params_1600mhz,
@@ -399,91 +413,6 @@ void enable_basic_uboot_clocks(void)
                         1);
 }
 
-/*
- * Enable non-essential clock domains, modules and
- * do some additional special settings needed
- */
-void enable_non_essential_clocks(void)
-{
-       u32 const clk_domains_non_essential[] = {
-               (*prcm)->cm_mpu_m3_clkstctrl,
-               (*prcm)->cm_ivahd_clkstctrl,
-               (*prcm)->cm_dsp_clkstctrl,
-               (*prcm)->cm_dss_clkstctrl,
-               (*prcm)->cm_sgx_clkstctrl,
-               (*prcm)->cm1_abe_clkstctrl,
-               (*prcm)->cm_c2c_clkstctrl,
-               (*prcm)->cm_cam_clkstctrl,
-               (*prcm)->cm_dss_clkstctrl,
-               (*prcm)->cm_sdma_clkstctrl,
-               0
-       };
-
-       u32 const clk_modules_hw_auto_non_essential[] = {
-               (*prcm)->cm_l3instr_l3_3_clkctrl,
-               (*prcm)->cm_l3instr_l3_instr_clkctrl,
-               (*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
-               (*prcm)->cm_l3init_hsi_clkctrl,
-               0
-       };
-
-       u32 const clk_modules_explicit_en_non_essential[] = {
-               (*prcm)->cm1_abe_aess_clkctrl,
-               (*prcm)->cm1_abe_pdm_clkctrl,
-               (*prcm)->cm1_abe_dmic_clkctrl,
-               (*prcm)->cm1_abe_mcasp_clkctrl,
-               (*prcm)->cm1_abe_mcbsp1_clkctrl,
-               (*prcm)->cm1_abe_mcbsp2_clkctrl,
-               (*prcm)->cm1_abe_mcbsp3_clkctrl,
-               (*prcm)->cm1_abe_slimbus_clkctrl,
-               (*prcm)->cm1_abe_timer5_clkctrl,
-               (*prcm)->cm1_abe_timer6_clkctrl,
-               (*prcm)->cm1_abe_timer7_clkctrl,
-               (*prcm)->cm1_abe_timer8_clkctrl,
-               (*prcm)->cm1_abe_wdt3_clkctrl,
-               (*prcm)->cm_l4per_gptimer9_clkctrl,
-               (*prcm)->cm_l4per_gptimer10_clkctrl,
-               (*prcm)->cm_l4per_gptimer11_clkctrl,
-               (*prcm)->cm_l4per_gptimer3_clkctrl,
-               (*prcm)->cm_l4per_gptimer4_clkctrl,
-               (*prcm)->cm_l4per_hdq1w_clkctrl,
-               (*prcm)->cm_l4per_mcbsp4_clkctrl,
-               (*prcm)->cm_l4per_mcspi2_clkctrl,
-               (*prcm)->cm_l4per_mcspi3_clkctrl,
-               (*prcm)->cm_l4per_mcspi4_clkctrl,
-               (*prcm)->cm_l4per_mmcsd3_clkctrl,
-               (*prcm)->cm_l4per_mmcsd4_clkctrl,
-               (*prcm)->cm_l4per_mmcsd5_clkctrl,
-               (*prcm)->cm_l4per_uart1_clkctrl,
-               (*prcm)->cm_l4per_uart2_clkctrl,
-               (*prcm)->cm_l4per_uart4_clkctrl,
-               (*prcm)->cm_wkup_keyboard_clkctrl,
-               (*prcm)->cm_wkup_wdtimer2_clkctrl,
-               (*prcm)->cm_cam_iss_clkctrl,
-               (*prcm)->cm_cam_fdif_clkctrl,
-               (*prcm)->cm_dss_dss_clkctrl,
-               (*prcm)->cm_sgx_sgx_clkctrl,
-               0
-       };
-
-       /* Enable optional functional clock for ISS */
-       setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
-
-       /* Enable all optional functional clocks of DSS */
-       setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
-
-       do_enable_clocks(clk_domains_non_essential,
-                        clk_modules_hw_auto_non_essential,
-                        clk_modules_explicit_en_non_essential,
-                        0);
-
-       /* Put camera module in no sleep mode */
-       clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
-                       MODULE_CLKCTRL_MODULEMODE_MASK,
-                       CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
-                       MODULE_CLKCTRL_MODULEMODE_SHIFT);
-}
-
 void hw_data_init(void)
 {
        u32 omap_rev = omap_revision();
@@ -498,6 +427,10 @@ void hw_data_init(void)
        break;
 
        case OMAP4430_ES2_0:
+       *dplls_data = &omap4430_dplls_es20;
+       *omap_vcores = &omap4430_volts;
+       break;
+
        case OMAP4430_ES2_1:
        case OMAP4430_ES2_2:
        case OMAP4430_ES2_3: