]> git.sur5r.net Git - u-boot/blobdiff - arch/arm/cpu/armv7/omap4/sdram_elpida.c
arm: ls102xa: workaround for cache coherency problem
[u-boot] / arch / arm / cpu / armv7 / omap4 / sdram_elpida.c
index e4c8316370955355f0506af6b46d1ee158e17ab3..4462c72c7a5d23e707ee4da33bcf7b0d75e321b5 100644 (file)
@@ -32,7 +32,7 @@
 
 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 
-static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
+const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
        .sdram_config_init              = 0x80000eb9,
        .sdram_config                   = 0x80001ab9,
        .ref_ctrl                       = 0x0000030c,
@@ -46,7 +46,7 @@ static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
        .emif_ddr_phy_ctlr_1            = 0x049ff808
 };
 
-static const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
+const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
        .sdram_config_init              = 0x80000eb1,
        .sdram_config                   = 0x80001ab1,
        .ref_ctrl                       = 0x000005cd,
@@ -121,8 +121,6 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
                *regs = &emif_regs_elpida_380_mhz_1cs;
        else if (omap4_rev == OMAP4430_ES2_0)
                *regs = &emif_regs_elpida_200_mhz_2cs;
-       else if (omap4_rev == OMAP4430_ES2_3)
-               *regs = &emif_regs_elpida_400_mhz_1cs;
        else if (omap4_rev < OMAP4470_ES1_0)
                *regs = &emif_regs_elpida_400_mhz_2cs;
        else
@@ -138,8 +136,6 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 
        if (omap_rev == OMAP4430_ES1_0)
                *dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
-       else if (omap_rev == OMAP4430_ES2_3)
-               *dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
        else if (omap_rev < OMAP4460_ES1_0)
                *dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
        else
@@ -321,3 +317,8 @@ void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
 {
        *regs = &mr_regs;
 }
+
+__weak const struct read_write_regs *get_bug_regs(u32 *iterations)
+{
+       return 0;
+}