imx6: isiotmx6ul: Add FEC support

[u-boot] / arch / arm / cpu / armv7 / psci.S

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index f80f6e20d1ecee25edf17a7a12f59081f997d198..95b962dadf0b2c380de57ce3dcdedfda91ff9caa 100644 (file)
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -187,7 +187,7 @@ ENDPROC(psci_get_cpu_id)
 .weak psci_get_cpu_id
 
 /* Imported from Linux kernel */
-LENTRY(v7_flush_dcache_all)
+ENTRY(psci_v7_flush_dcache_all)
        stmfd   sp!, {r4-r5, r7, r9-r11, lr}
        dmb                                     @ ensure ordering with previous memory accesses
        mrc     p15, 1, r0, c0, c0, 1           @ read clidr
@@ -234,7 +234,7 @@ finished:
        isb
        ldmfd   sp!, {r4-r5, r7, r9-r11, lr}
        bx      lr
-ENDPROC(v7_flush_dcache_all)
+ENDPROC(psci_v7_flush_dcache_all)
 
 ENTRY(psci_disable_smp)
        mrc     p15, 0, r0, c1, c0, 1           @ ACTLR
@@ -258,13 +258,17 @@ ENDPROC(psci_enable_smp)
 ENTRY(psci_cpu_off_common)
        push    {lr}
 
+       bl      psci_v7_flush_dcache_all
+
+       clrex                                   @ Why???
+
        mrc     p15, 0, r0, c1, c0, 0           @ SCTLR
        bic     r0, r0, #(1 << 2)               @ Clear C bit
        mcr     p15, 0, r0, c1, c0, 0           @ SCTLR
        isb
        dsb
 
-       bl      v7_flush_dcache_all
+       bl      psci_v7_flush_dcache_all
 
        clrex                                   @ Why???