Merge branch 'rmobile' of git://git.denx.de/u-boot-sh

[u-boot] / arch / arm / cpu / armv7 / rmobile / pfc-r8a7794.c

diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c
index e1236633337629f6c0a7e4bcc79497fb8562baac..7ea5edc2e506ef9d2b24dd887aefa6e57636d530 100644 (file)
--- a/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c
+++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c
@@ -151,8 +151,18 @@ enum {
        FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
        FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
 
+       /* IPSR0 */
+       FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK,
+       FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1,
+       FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3,
+       FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD,
+       FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B,
+       FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B,
+       FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4,
+       FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D,
+
        /*
-        * From IPSR0 to IPSR5 have been removed because they does not use.
+        * From IPSR1 to IPSR5 have been removed because they does not use.
         */
 
        /* IPSR6 */
@@ -285,8 +295,20 @@ enum {
        SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
        SD1_DATA2_MARK, SD1_DATA3_MARK,
 
+       /* IPSR0 */
+       SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK,
+       MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK,
+       SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK,
+       SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK,
+       MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK,
+       CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK,
+       CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK,
+       SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK,
+       SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK,
+       SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK,
+
        /*
-        * From IPSR0 to IPSR5 have been removed because they does not use.
+        * From IPSR1 to IPSR5 have been removed because they does not use.
         */
 
        /* IPSR6 */
@@ -399,8 +421,55 @@ static pinmux_enum_t pinmux_data[] = {
        PINMUX_DATA(SD1_DATA2_MARK, FN_SD1_DATA2),
        PINMUX_DATA(SD1_DATA3_MARK, FN_SD1_DATA3),
 
+       /* IPSR0 */
+       PINMUX_IPSR_DATA(IP0_0, SD1_CD),
+       PINMUX_IPSR_MODSEL_DATA(IP0_0, CAN0_RX, SEL_CAN0_0),
+       PINMUX_IPSR_DATA(IP0_9_8, SD1_WP),
+       PINMUX_IPSR_DATA(IP0_9_8, IRQ7),
+       PINMUX_IPSR_MODSEL_DATA(IP0_9_8, CAN0_TX, SEL_CAN0_0),
+       PINMUX_IPSR_DATA(IP0_10, MMC_CLK),
+       PINMUX_IPSR_DATA(IP0_10, SD2_CLK),
+       PINMUX_IPSR_DATA(IP0_11, MMC_CMD),
+       PINMUX_IPSR_DATA(IP0_11, SD2_CMD),
+       PINMUX_IPSR_DATA(IP0_12, MMC_D0),
+       PINMUX_IPSR_DATA(IP0_12, SD2_DATA0),
+       PINMUX_IPSR_DATA(IP0_13, MMC_D1),
+       PINMUX_IPSR_DATA(IP0_13, SD2_DATA1),
+       PINMUX_IPSR_DATA(IP0_14, MMC_D2),
+       PINMUX_IPSR_DATA(IP0_14, SD2_DATA2),
+       PINMUX_IPSR_DATA(IP0_15, MMC_D3),
+       PINMUX_IPSR_DATA(IP0_15, SD2_DATA3),
+       PINMUX_IPSR_DATA(IP0_16, MMC_D4),
+       PINMUX_IPSR_DATA(IP0_16, SD2_CD),
+       PINMUX_IPSR_DATA(IP0_17, MMC_D5),
+       PINMUX_IPSR_DATA(IP0_17, SD2_WP),
+       PINMUX_IPSR_DATA(IP0_19_18, MMC_D6),
+       PINMUX_IPSR_MODSEL_DATA(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
+       PINMUX_IPSR_MODSEL_DATA(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
+       PINMUX_IPSR_MODSEL_DATA(IP0_19_18, CAN1_RX, SEL_CAN1_0),
+       PINMUX_IPSR_DATA(IP0_21_20, MMC_D7),
+       PINMUX_IPSR_MODSEL_DATA(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
+       PINMUX_IPSR_MODSEL_DATA(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
+       PINMUX_IPSR_MODSEL_DATA(IP0_21_20, CAN1_TX, SEL_CAN1_0),
+       PINMUX_IPSR_DATA(IP0_23_22, D0),
+       PINMUX_IPSR_MODSEL_DATA(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
+       PINMUX_IPSR_DATA(IP0_23_22, IRQ4),
+       PINMUX_IPSR_DATA(IP0_24, D1),
+       PINMUX_IPSR_MODSEL_DATA(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
+       PINMUX_IPSR_DATA(IP0_25, D2),
+       PINMUX_IPSR_MODSEL_DATA(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1),
+       PINMUX_IPSR_DATA(IP0_27_26, D3),
+       PINMUX_IPSR_MODSEL_DATA(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1),
+       PINMUX_IPSR_MODSEL_DATA(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1),
+       PINMUX_IPSR_DATA(IP0_29_28, D4),
+       PINMUX_IPSR_MODSEL_DATA(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1),
+       PINMUX_IPSR_MODSEL_DATA(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1),
+       PINMUX_IPSR_DATA(IP0_31_30, D5),
+       PINMUX_IPSR_MODSEL_DATA(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1),
+       PINMUX_IPSR_MODSEL_DATA(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3),
+
        /*
-        * From IPSR0 to IPSR5 have been removed because they does not use.
+        * From IPSR1 to IPSR5 have been removed because they does not use.
         */
 
        /* IPSR6 */
@@ -674,8 +743,23 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_FN(SD1_CLK), GPIO_FN(SD1_CMD), GPIO_FN(SD1_DATA0),
        GPIO_FN(SD1_DATA1), GPIO_FN(SD1_DATA2), GPIO_FN(SD1_DATA3),
 
+       /* IPSR0 */
+       GPIO_FN(SD1_CD), GPIO_FN(CAN0_RX), GPIO_FN(SD1_WP), GPIO_FN(IRQ7),
+       GPIO_FN(CAN0_TX), GPIO_FN(MMC_CLK), GPIO_FN(SD2_CLK), GPIO_FN(MMC_CMD),
+       GPIO_FN(SD2_CMD), GPIO_FN(MMC_D0), GPIO_FN(SD2_DATA0), GPIO_FN(MMC_D1),
+       GPIO_FN(SD2_DATA1), GPIO_FN(MMC_D2), GPIO_FN(SD2_DATA2),
+       GPIO_FN(MMC_D3), GPIO_FN(SD2_DATA3), GPIO_FN(MMC_D4),
+       GPIO_FN(SD2_CD), GPIO_FN(MMC_D5), GPIO_FN(SD2_WP), GPIO_FN(MMC_D6),
+       GPIO_FN(SCIF0_RXD), GPIO_FN(I2C2_SCL_B), GPIO_FN(CAN1_RX),
+       GPIO_FN(MMC_D7), GPIO_FN(SCIF0_TXD), GPIO_FN(I2C2_SDA_B),
+       GPIO_FN(CAN1_TX), GPIO_FN(D0), GPIO_FN(SCIFA3_SCK_B), GPIO_FN(IRQ4),
+       GPIO_FN(D1), GPIO_FN(SCIFA3_RXD_B), GPIO_FN(D2), GPIO_FN(SCIFA3_TXD_B),
+       GPIO_FN(D3), GPIO_FN(I2C3_SCL_B), GPIO_FN(SCIF5_RXD_B), GPIO_FN(D4),
+       GPIO_FN(I2C3_SDA_B), GPIO_FN(SCIF5_TXD_B), GPIO_FN(D5),
+       GPIO_FN(SCIF4_RXD_B), GPIO_FN(I2C0_SCL_D),
+
        /*
-        * From IPSR0 to IPSR5 have been removed because they does not use
+        * From IPSR1 to IPSR5 have been removed because they does not use.
         */
 
        /* IPSR6 */
@@ -1017,9 +1101,63 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                GP_6_1_FN, FN_SD0_CMD,
                GP_6_0_FN, FN_SD0_CLK }
        },
+       { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
+                            2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
+                            2, 1, 1, 1, 1, 1, 1, 1, 1) {
+               /* IP0_31_30 [2] */
+               FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
+               /* IP0_29_28 [2] */
+               FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0,
+               /* IP0_27_26 [2] */
+               FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0,
+               /* IP0_25 [1] */
+               FN_D2, FN_SCIFA3_TXD_B,
+               /* IP0_24 [1] */
+               FN_D1, FN_SCIFA3_RXD_B,
+               /* IP0_23_22 [2] */
+               FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0,
+               /* IP0_21_20 [2] */
+               FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX,
+               /* IP0_19_18 [2] */
+               FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX,
+               /* IP0_17 [1] */
+               FN_MMC_D5, FN_SD2_WP,
+               /* IP0_16 [1] */
+               FN_MMC_D4, FN_SD2_CD,
+               /* IP0_15 [1] */
+               FN_MMC_D3, FN_SD2_DATA3,
+               /* IP0_14 [1] */
+               FN_MMC_D2, FN_SD2_DATA2,
+               /* IP0_13 [1] */
+               FN_MMC_D1, FN_SD2_DATA1,
+               /* IP0_12 [1] */
+               FN_MMC_D0, FN_SD2_DATA0,
+               /* IP0_11 [1] */
+               FN_MMC_CMD, FN_SD2_CMD,
+               /* IP0_10 [1] */
+               FN_MMC_CLK, FN_SD2_CLK,
+               /* IP0_9_8 [2] */
+               FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
+               /* IP0_7 [1] */
+               0, 0,
+               /* IP0_6 [1] */
+               0, 0,
+               /* IP0_5 [1] */
+               0, 0,
+               /* IP0_4 [1] */
+               0, 0,
+               /* IP0_3 [1] */
+               0, 0,
+               /* IP0_2 [1] */
+               0, 0,
+               /* IP0_1 [1] */
+               0, 0,
+               /* IP0_0 [1] */
+               FN_SD1_CD, FN_CAN0_RX, }
+       },
 
        /*
-        * From IPSR0 to IPSR5 have been removed because they does not use.
+        * From IPSR1 to IPSR5 have been removed because they does not use.
         */
 
        { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,