ARM: vf610: Enable caches

[u-boot] / arch / arm / cpu / armv7 / start.S

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 098a83ab7145bd324e6db9c20e0a5aea95c70970..5ed0f45a26614159328928fbdeac84f692f54d71 100644 (file)
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -15,7 +15,6 @@
 
 #include <asm-offsets.h>
 #include <config.h>
-#include <version.h>
 #include <asm/system.h>
 #include <linux/linkage.h>
 
@@ -54,8 +53,7 @@ save_boot_params_ret:
  * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
  * Continue to use ROM code vector only in OMAP4 spl)
  */
-#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) && \
-               !defined(CONFIG_SPL_FEL)
+#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
        /* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */
        mrc     p15, 0, r0, c1, c0, 0   @ Read CP15 SCTLR Register
        bic     r0, #CR_V               @ V = 0
@@ -68,9 +66,7 @@ save_boot_params_ret:
 
        /* the mask ROM code should have PLL and others stable */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
-#ifndef CONFIG_SPL_FEL
        bl      cpu_init_cp15
-#endif
        bl      cpu_init_crit
 #endif
 
@@ -169,7 +165,69 @@ ENTRY(cpu_init_cp15)
        mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
 #endif
 
-       mov     pc, lr                  @ back to my caller
+       mov     r5, lr                  @ Store my Caller
+       mrc     p15, 0, r1, c0, c0, 0   @ r1 has Read Main ID Register (MIDR)
+       mov     r3, r1, lsr #20         @ get variant field
+       and     r3, r3, #0xf            @ r3 has CPU variant
+       and     r4, r1, #0xf            @ r4 has CPU revision
+       mov     r2, r3, lsl #4          @ shift variant field for combined value
+       orr     r2, r4, r2              @ r2 has combined CPU variant + revision
+
+#ifdef CONFIG_ARM_ERRATA_798870
+       cmp     r2, #0x30               @ Applies to lower than R3p0
+       bge     skip_errata_798870      @ skip if not affected rev
+       cmp     r2, #0x20               @ Applies to including and above R2p0
+       blt     skip_errata_798870      @ skip if not affected rev
+
+       mrc     p15, 1, r0, c15, c0, 0  @ read l2 aux ctrl reg
+       orr     r0, r0, #1 << 7         @ Enable hazard-detect timeout
+       push    {r1-r5}                 @ Save the cpu info registers
+       bl      v7_arch_cp15_set_l2aux_ctrl
+       isb                             @ Recommended ISB after l2actlr update
+       pop     {r1-r5}                 @ Restore the cpu info - fall through
+skip_errata_798870:
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_454179
+       cmp     r2, #0x21               @ Only on < r2p1
+       bge     skip_errata_454179
+
+       mrc     p15, 0, r0, c1, c0, 1   @ Read ACR
+       orr     r0, r0, #(0x3 << 6)     @ Set DBSM(BIT7) and IBE(BIT6) bits
+       push    {r1-r5}                 @ Save the cpu info registers
+       bl      v7_arch_cp15_set_acr
+       pop     {r1-r5}                 @ Restore the cpu info - fall through
+
+skip_errata_454179:
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_430973
+       cmp     r2, #0x21               @ Only on < r2p1
+       bge     skip_errata_430973
+
+       mrc     p15, 0, r0, c1, c0, 1   @ Read ACR
+       orr     r0, r0, #(0x1 << 6)     @ Set IBE bit
+       push    {r1-r5}                 @ Save the cpu info registers
+       bl      v7_arch_cp15_set_acr
+       pop     {r1-r5}                 @ Restore the cpu info - fall through
+
+skip_errata_430973:
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_621766
+       cmp     r2, #0x21               @ Only on < r2p1
+       bge     skip_errata_621766
+
+       mrc     p15, 0, r0, c1, c0, 1   @ Read ACR
+       orr     r0, r0, #(0x1 << 5)     @ Set L1NEON bit
+       push    {r1-r5}                 @ Save the cpu info registers
+       bl      v7_arch_cp15_set_acr
+       pop     {r1-r5}                 @ Restore the cpu info - fall through
+
+skip_errata_621766:
+#endif
+
+       mov     pc, r5                  @ back to my caller
 ENDPROC(cpu_init_cp15)
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT