ARM: vf610: Enable caches

[u-boot] / arch / arm / cpu / armv7 / start.S

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 8483687879ed70054deb33cc4f56e22780ac1544..5ed0f45a26614159328928fbdeac84f692f54d71 100644 (file)
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -15,7 +15,6 @@
 
 #include <asm-offsets.h>
 #include <config.h>
-#include <version.h>
 #include <asm/system.h>
 #include <linux/linkage.h>
 
@@ -200,6 +199,32 @@ skip_errata_798870:
        pop     {r1-r5}                 @ Restore the cpu info - fall through
 
 skip_errata_454179:
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_430973
+       cmp     r2, #0x21               @ Only on < r2p1
+       bge     skip_errata_430973
+
+       mrc     p15, 0, r0, c1, c0, 1   @ Read ACR
+       orr     r0, r0, #(0x1 << 6)     @ Set IBE bit
+       push    {r1-r5}                 @ Save the cpu info registers
+       bl      v7_arch_cp15_set_acr
+       pop     {r1-r5}                 @ Restore the cpu info - fall through
+
+skip_errata_430973:
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_621766
+       cmp     r2, #0x21               @ Only on < r2p1
+       bge     skip_errata_621766
+
+       mrc     p15, 0, r0, c1, c0, 1   @ Read ACR
+       orr     r0, r0, #(0x1 << 5)     @ Set L1NEON bit
+       push    {r1-r5}                 @ Save the cpu info registers
+       bl      v7_arch_cp15_set_acr
+       pop     {r1-r5}                 @ Restore the cpu info - fall through
+
+skip_errata_621766:
 #endif
 
        mov     pc, r5                  @ back to my caller