Merge branch 'master' of git://git.denx.de/u-boot-ubi

[u-boot] / arch / arm / cpu / armv7 / start.S

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 5ed0f45a26614159328928fbdeac84f692f54d71..691e5d3fe165c79af45826e24cda182560333e67 100644 (file)
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -22,10 +22,9 @@
  *
  * Startup Code (reset vector)
  *
- * do important init only if we don't start from memory!
- * setup Memory and board specific bits prior to relocation.
- * relocate armboot to ram
- * setup stack
+ * Do important init only if we don't start from memory!
+ * Setup memory and board specific bits prior to relocation.
+ * Relocate armboot to ram. Setup stack.
  *
  *************************************************************************/
 
@@ -67,7 +66,9 @@ save_boot_params_ret:
        /* the mask ROM code should have PLL and others stable */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
        bl      cpu_init_cp15
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
        bl      cpu_init_crit
+#endif
 #endif
 
        bl      _main
@@ -188,6 +189,27 @@ ENTRY(cpu_init_cp15)
 skip_errata_798870:
 #endif
 
+#ifdef CONFIG_ARM_ERRATA_801819
+       cmp     r2, #0x24               @ Applies to lt including R2p4
+       bgt     skip_errata_801819      @ skip if not affected rev
+       cmp     r2, #0x20               @ Applies to including and above R2p0
+       blt     skip_errata_801819      @ skip if not affected rev
+       mrc     p15, 0, r0, c0, c0, 6   @ pick up REVIDR reg
+       and     r0, r0, #1 << 3         @ check REVIDR[3]
+       cmp     r0, #1 << 3
+       beq     skip_errata_801819      @ skip erratum if REVIDR[3] is set
+
+       mrc     p15, 0, r0, c1, c0, 1   @ read auxilary control register
+       orr     r0, r0, #3 << 27        @ Disables streaming. All write-allocate
+                                       @ lines allocate in the L1 or L2 cache.
+       orr     r0, r0, #3 << 25        @ Disables streaming. All write-allocate
+                                       @ lines allocate in the L1 cache.
+       push    {r1-r5}                 @ Save the cpu info registers
+       bl      v7_arch_cp15_set_acr
+       pop     {r1-r5}                 @ Restore the cpu info - fall through
+skip_errata_801819:
+#endif
+
 #ifdef CONFIG_ARM_ERRATA_454179
        cmp     r2, #0x21               @ Only on < r2p1
        bge     skip_errata_454179
@@ -230,7 +252,8 @@ skip_errata_621766:
        mov     pc, r5                  @ back to my caller
 ENDPROC(cpu_init_cp15)
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
+       !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
 /*************************************************************************
  *
  * CPU_init_critical registers