]> git.sur5r.net Git - u-boot/blobdiff - arch/arm/cpu/armv7/start.S
ARM: Add workaround for Cortex-A9 errata 794072
[u-boot] / arch / arm / cpu / armv7 / start.S
index 5aac7736444c5e7101d680478f23be93c16f7e38..f3830c847161a0dc891cd3ef1fc0a6226347be18 100644 (file)
@@ -70,29 +70,6 @@ _end_vect:
  *
  *************************************************************************/
 
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-       .word   CONFIG_SPL_TEXT_BASE
-#else
-       .word   CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-       .word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-       .word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
-       .word _end - _start
-
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
@@ -228,7 +205,7 @@ ENTRY(cpu_init_cp15)
        mcr     p15, 0, r0, c1, c0, 0   @ write system control register
 #endif
 
-#ifdef CONFIG_ARM_ERRATA_742230
+#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072))
        mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
        orr     r0, r0, #1 << 4         @ set bit #4
        mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register