omap: gpmc: 'nandecc sw' can use HAM1 or BCH8

[u-boot] / arch / arm / cpu / armv7 / sunxi / dram_sun4i.c

diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c
index dc9fdb930b6e5c51c2d7252f7b4511439c3f33a2..c736fa3b474f5bbb3ed704fea566985c6c9b1011 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c
@@ -35,25 +35,12 @@
 #define CPU_CFG_CHIP_REV_C2 0x2
 #define CPU_CFG_CHIP_REV_B 0x3
 
-/*
- * Wait up to 1s for value to be set in given part of reg.
- */
-static void await_completion(u32 *reg, u32 mask, u32 val)
-{
-       unsigned long tmo = timer_get_us() + 1000000;
-
-       while ((readl(reg) & mask) != val) {
-               if (timer_get_us() > tmo)
-                       panic("Timeout initialising DRAM\n");
-       }
-}
-
 /*
  * Wait up to 1s for mask to be clear in given reg.
  */
 static inline void await_bits_clear(u32 *reg, u32 mask)
 {
-       await_completion(reg, mask, 0);
+       mctl_await_completion(reg, mask, 0);
 }
 
 /*
@@ -61,7 +48,7 @@ static inline void await_bits_clear(u32 *reg, u32 mask)
  */
 static inline void await_bits_set(u32 *reg, u32 mask)
 {
-       await_completion(reg, mask, mask);
+       mctl_await_completion(reg, mask, mask);
 }
 
 /*
@@ -428,9 +415,9 @@ static void dramc_clock_output_en(u32 on)
 #ifdef CONFIG_MACH_SUN4I
        struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
        if (on)
-               setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
+               setbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT);
        else
-               clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
+               clrbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT);
 #endif
 }