omap: gpmc: 'nandecc sw' can use HAM1 or BCH8

[u-boot] / arch / arm / cpu / armv7 / sunxi / dram_sun4i.c

diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c
index ec8aaa7d48e6a92ca3c94825b034d495dd00a87c..c736fa3b474f5bbb3ed704fea566985c6c9b1011 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c
@@ -35,25 +35,12 @@
 #define CPU_CFG_CHIP_REV_C2 0x2
 #define CPU_CFG_CHIP_REV_B 0x3
 
-/*
- * Wait up to 1s for value to be set in given part of reg.
- */
-static void await_completion(u32 *reg, u32 mask, u32 val)
-{
-       unsigned long tmo = timer_get_us() + 1000000;
-
-       while ((readl(reg) & mask) != val) {
-               if (timer_get_us() > tmo)
-                       panic("Timeout initialising DRAM\n");
-       }
-}
-
 /*
  * Wait up to 1s for mask to be clear in given reg.
  */
 static inline void await_bits_clear(u32 *reg, u32 mask)
 {
-       await_completion(reg, mask, 0);
+       mctl_await_completion(reg, mask, 0);
 }
 
 /*
@@ -61,7 +48,7 @@ static inline void await_bits_clear(u32 *reg, u32 mask)
  */
 static inline void await_bits_set(u32 *reg, u32 mask)
 {
-       await_completion(reg, mask, mask);
+       mctl_await_completion(reg, mask, mask);
 }
 
 /*