omap: gpmc: 'nandecc sw' can use HAM1 or BCH8

[u-boot] / arch / arm / cpu / armv7 / sunxi / prcm.c

diff --git a/arch/arm/cpu/armv7/sunxi/prcm.c b/arch/arm/cpu/armv7/sunxi/prcm.c
index 7b3ee893026b4c780cd81f88dda8fb7aef5e0395..19b4938dc9742c0ed453529838821bc17eb8747c 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/prcm.c
+++ b/arch/arm/cpu/armv7/sunxi/prcm.c
@@ -21,13 +21,15 @@
 #include <asm/arch/prcm.h>
 #include <asm/arch/sys_proto.h>
 
-void prcm_init_apb0(void)
+/* APB0 clock gate and reset bit offsets are the same. */
+void prcm_apb0_enable(u32 flags)
 {
        struct sunxi_prcm_reg *prcm =
                (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
 
-       setbits_le32(&prcm->apb0_gate, PRCM_APB0_GATE_P2WI |
-                                      PRCM_APB0_GATE_PIO);
-       setbits_le32(&prcm->apb0_reset, PRCM_APB0_RESET_P2WI |
-                                       PRCM_APB0_RESET_PIO);
+       /* open the clock for module */
+       setbits_le32(&prcm->apb0_gate, flags);
+
+       /* deassert reset for module */
+       setbits_le32(&prcm->apb0_reset, flags);
 }