env: Rename setenv() to env_set()

[u-boot] / arch / arm / cpu / armv7 / vf610 / generic.c

diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c
index 3bdc2211e7953c6e74a4ce6de98da71261ed984e..88f3f4dd163348cf47508520cffec2119afc2638 100644 (file)
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -9,6 +9,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/mach-imx/sys_proto.h>
 #include <netdev.h>
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
@@ -198,6 +199,16 @@ static u32 get_i2c_clk(void)
        return get_ipg_clk();
 }
 
+static u32 get_dspi_clk(void)
+{
+       return get_ipg_clk();
+}
+
+u32 get_lpuart_clk(void)
+{
+       return get_uart_clk();
+}
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
        switch (clk) {
@@ -215,6 +226,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
                return get_fec_clk();
        case MXC_I2C_CLK:
                return get_i2c_clk();
+       case MXC_DSPI_CLK:
+               return get_dspi_clk();
        default:
                break;
        }
@@ -259,6 +272,11 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 }
 #endif
 
+u32 get_cpu_rev(void)
+{
+       return MXC_CPU_VF610 << 12;
+}
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 static char *get_reset_cause(void)
 {
@@ -309,9 +327,9 @@ int arch_misc_init(void)
 {
        char soc[6];
 
-       strcat(soc, "vf");
+       strcpy(soc, "vf");
        strcat(soc, soc_type);
-       setenv("soc", soc);
+       env_set("soc", soc);
 
        return 0;
 }
@@ -342,3 +360,19 @@ int get_clocks(void)
 #endif
        return 0;
 }
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+       enum dcache_option option = DCACHE_WRITETHROUGH;
+#else
+       enum dcache_option option = DCACHE_WRITEBACK;
+#endif
+       dcache_enable();
+       icache_enable();
+
+    /* Enable caching on OCRAM */
+       mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, option);
+}
+#endif