clock_am43xx:Set the MAC clock to /5 for OPP100

[u-boot] / arch / arm / cpu / armv7 / zynq / cpu.c

diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index 5d505dd4864e94ba684f5824d217359399be8e4a..914b1feb6833310144d229c307b8130218d00f02 100644 (file)
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -10,14 +10,13 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/hardware.h>
 
-void lowlevel_init(void)
-{
-}
+#define ZYNQ_SILICON_VER_MASK  0xF0000000
+#define ZYNQ_SILICON_VER_SHIFT 28
 
 int arch_cpu_init(void)
 {
        zynq_slcr_unlock();
-
+#ifndef CONFIG_SPL_BUILD
        /* Device config APB, unlock the PCAP */
        writel(0x757BDF0D, &devcfg_base->unlock);
        writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
@@ -35,13 +34,23 @@ int arch_cpu_init(void)
        /* Urgent write, ports S2/S3 */
        writel(0xC, &slcr_base->ddr_urgent);
 #endif
-
+#endif
        zynq_clk_early_init();
        zynq_slcr_lock();
 
        return 0;
 }
 
+unsigned int zynq_get_silicon_version(void)
+{
+       unsigned int ver;
+
+       ver = (readl(&devcfg_base->mctrl) &
+              ZYNQ_SILICON_VER_MASK) >> ZYNQ_SILICON_VER_SHIFT;
+
+       return ver;
+}
+
 void reset_cpu(ulong addr)
 {
        zynq_slcr_cpu_reset();