clock_am43xx:Set the MAC clock to /5 for OPP100

[u-boot] / arch / arm / cpu / armv7 / zynq / slcr.c

diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index 51894f923975d575b00ab0523ce2923e30b57e3d..2521589c07e9cf0c07a2f59990a521aafcfea7c8 100644 (file)
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -14,6 +14,8 @@
 #define SLCR_LOCK_MAGIC                0x767B
 #define SLCR_UNLOCK_MAGIC      0xDF0D
 
+#define SLCR_USB_L1_SEL                        0x04
+
 #define SLCR_IDCODE_MASK       0x1F000
 #define SLCR_IDCODE_SHIFT      12
 
@@ -34,7 +36,29 @@ struct zynq_slcr_mio_get_status {
        u32 check_val;
 };
 
+static const int usb0_pins[] = {
+       28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
+};
+
+static const int usb1_pins[] = {
+       40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51
+};
+
 static const struct zynq_slcr_mio_get_status mio_periphs[] = {
+       {
+               "usb0",
+               usb0_pins,
+               ARRAY_SIZE(usb0_pins),
+               SLCR_USB_L1_SEL,
+               SLCR_USB_L1_SEL,
+       },
+       {
+               "usb1",
+               usb1_pins,
+               ARRAY_SIZE(usb1_pins),
+               SLCR_USB_L1_SEL,
+               SLCR_USB_L1_SEL,
+       },
 };
 
 static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
@@ -108,7 +132,7 @@ void zynq_slcr_devcfg_disable(void)
        zynq_slcr_unlock();
 
        /* Disable AXI interface by asserting FPGA resets */
-       writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
+       writel(0xF, &slcr_base->fpga_rst_ctrl);
 
        /* Set Level Shifters DT618760 */
        writel(0xA, &slcr_base->lvl_shftr_en);