armv8: layerscape: Update early MMU for DDR after initialization

[u-boot] / arch / arm / cpu / armv8 / Kconfig

diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 472b2ba188288c512d0077026a42fc2e1328bb69..0188b95e99fa64672e88b3ad6289ab26825339fc 100644 (file)
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -30,8 +30,10 @@ config ARMV8_SPIN_TABLE
          To use this feature, you must do:
            - Specify enable-method = "spin-table" in each CPU node in the
              Device Tree you are using to boot the kernel
-           - Let secondary CPUs in U-Boot (in a board specific manner)
-             before the master CPU jumps to the kernel
+           - Bring secondary CPUs into U-Boot proper in a board specific
+             manner.  This must be done *after* relocation.  Otherwise, the
+             secondary CPUs will spin in unprotected memory area because the
+             master CPU protects the relocated spin code.
 
          U-Boot automatically does:
            - Set "cpu-release-addr" property of each CPU node
@@ -39,6 +41,47 @@ config ARMV8_SPIN_TABLE
            - Reserve the code for the spin-table and the release address
              via a /memreserve/ region in the Device Tree.
 
+menu "ARMv8 secure monitor firmware"
+config ARMV8_SEC_FIRMWARE_SUPPORT
+       bool "Enable ARMv8 secure monitor firmware framework support"
+       select OF_LIBFDT
+       select FIT
+       help
+         This framework is aimed at making secure monitor firmware load
+         process brief.
+         Note: Only FIT format image is supported.
+         You should prepare and provide the below information:
+           - Address of secure firmware.
+           - Address to hold the return address from secure firmware.
+           - Secure firmware FIT image related information.
+             Such as: SEC_FIRMWARE_FIT_IMAGE and SEC_FIRMEWARE_FIT_CNF_NAME
+           - The target exception level that secure monitor firmware will
+             return to.
+
+config SPL_ARMV8_SEC_FIRMWARE_SUPPORT
+       bool "Enable ARMv8 secure monitor firmware framework support for SPL"
+       select SPL_OF_LIBFDT
+       select SPL_FIT
+       help
+         Say Y here to support this framework in SPL phase.
+
+config SEC_FIRMWARE_ARMV8_PSCI
+       bool "PSCI implementation in secure monitor firmware"
+       depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
+       help
+         This config enables the ARMv8 PSCI implementation in secure monitor
+         firmware. This is a private PSCI implementation and different from
+         those implemented under the common ARMv8 PSCI framework.
+
+config ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT
+       bool "ARMv8 secure monitor firmware ERET address byteorder swap"
+       depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
+       help
+         Say Y here when the endianness of the register or memory holding the
+         Secure firmware exception return address is different with core's.
+
+endmenu
+
 config PSCI_RESET
        bool "Use PSCI for reset and shutdown"
        default y