armv8: layerscape: Update early MMU for DDR after initialization

[u-boot] / arch / arm / cpu / armv8 / Kconfig

diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 7ef9c2fc523963531e9023aa884fc199d08b81e2..0188b95e99fa64672e88b3ad6289ab26825339fc 100644 (file)
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -30,8 +30,10 @@ config ARMV8_SPIN_TABLE
          To use this feature, you must do:
            - Specify enable-method = "spin-table" in each CPU node in the
              Device Tree you are using to boot the kernel
-           - Let secondary CPUs in U-Boot (in a board specific manner)
-             before the master CPU jumps to the kernel
+           - Bring secondary CPUs into U-Boot proper in a board specific
+             manner.  This must be done *after* relocation.  Otherwise, the
+             secondary CPUs will spin in unprotected memory area because the
+             master CPU protects the relocated spin code.
 
          U-Boot automatically does:
            - Set "cpu-release-addr" property of each CPU node
@@ -63,6 +65,14 @@ config SPL_ARMV8_SEC_FIRMWARE_SUPPORT
        help
          Say Y here to support this framework in SPL phase.
 
+config SEC_FIRMWARE_ARMV8_PSCI
+       bool "PSCI implementation in secure monitor firmware"
+       depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
+       help
+         This config enables the ARMv8 PSCI implementation in secure monitor
+         firmware. This is a private PSCI implementation and different from
+         those implemented under the common ARMv8 PSCI framework.
+
 config ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT
        bool "ARMv8 secure monitor firmware ERET address byteorder swap"
        depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT