SPDX: Convert all of our single license tags to Linux Kernel style

[u-boot] / arch / arm / cpu / armv8 / cache.S

diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index f1deaa723024e629c8a89aaee9c21bad0dff4a60..443d94c262a09d15b7358d5e27f236b9faf0d02a 100644 (file)
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -1,10 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2013
  * David Feng <fenghua@phytium.com.cn>
  *
  * This file is based on sample code from ARMv8 ARM.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <asm-offsets.h>
@@ -22,6 +21,7 @@
  * x1: 0 clean & invalidate, 1 invalidate only
  * x2~x9: clobbered
  */
+.pushsection .text.__asm_dcache_level, "ax"
 ENTRY(__asm_dcache_level)
        lsl     x12, x0, #1
        msr     csselr_el1, x12         /* select cache level */
@@ -58,6 +58,7 @@ loop_way:
 
        ret
 ENDPROC(__asm_dcache_level)
+.popsection
 
 /*
  * void __asm_flush_dcache_all(int invalidate_only)
@@ -66,6 +67,7 @@ ENDPROC(__asm_dcache_level)
  *
  * flush or invalidate all data cache by SET/WAY.
  */
+.pushsection .text.__asm_dcache_all, "ax"
 ENTRY(__asm_dcache_all)
        mov     x1, x0
        dsb     sy
@@ -102,16 +104,21 @@ skip:
 finished:
        ret
 ENDPROC(__asm_dcache_all)
+.popsection
 
+.pushsection .text.__asm_flush_dcache_all, "ax"
 ENTRY(__asm_flush_dcache_all)
        mov     x0, #0
        b       __asm_dcache_all
 ENDPROC(__asm_flush_dcache_all)
+.popsection
 
+.pushsection .text.__asm_invalidate_dcache_all, "ax"
 ENTRY(__asm_invalidate_dcache_all)
        mov     x0, #0x1
        b       __asm_dcache_all
 ENDPROC(__asm_invalidate_dcache_all)
+.popsection
 
 /*
  * void __asm_flush_dcache_range(start, end)
@@ -121,6 +128,7 @@ ENDPROC(__asm_invalidate_dcache_all)
  * x0: start address
  * x1: end address
  */
+.pushsection .text.__asm_flush_dcache_range, "ax"
 ENTRY(__asm_flush_dcache_range)
        mrs     x3, ctr_el0
        lsr     x3, x3, #16
@@ -138,41 +146,77 @@ ENTRY(__asm_flush_dcache_range)
        dsb     sy
        ret
 ENDPROC(__asm_flush_dcache_range)
+.popsection
+/*
+ * void __asm_invalidate_dcache_range(start, end)
+ *
+ * invalidate data cache in the range
+ *
+ * x0: start address
+ * x1: end address
+ */
+.pushsection .text.__asm_invalidate_dcache_range, "ax"
+ENTRY(__asm_invalidate_dcache_range)
+       mrs     x3, ctr_el0
+       ubfm    x3, x3, #16, #19
+       mov     x2, #4
+       lsl     x2, x2, x3              /* cache line size */
+
+       /* x2 <- minimal cache line size in cache system */
+       sub     x3, x2, #1
+       bic     x0, x0, x3
+1:     dc      ivac, x0        /* invalidate data or unified cache */
+       add     x0, x0, x2
+       cmp     x0, x1
+       b.lo    1b
+       dsb     sy
+       ret
+ENDPROC(__asm_invalidate_dcache_range)
+.popsection
 
 /*
  * void __asm_invalidate_icache_all(void)
  *
  * invalidate all tlb entries.
  */
+.pushsection .text.__asm_invalidate_icache_all, "ax"
 ENTRY(__asm_invalidate_icache_all)
        ic      ialluis
        isb     sy
        ret
 ENDPROC(__asm_invalidate_icache_all)
+.popsection
 
+.pushsection .text.__asm_invalidate_l3_dcache, "ax"
 ENTRY(__asm_invalidate_l3_dcache)
        mov     x0, #0                  /* return status as success */
        ret
 ENDPROC(__asm_invalidate_l3_dcache)
        .weak   __asm_invalidate_l3_dcache
+.popsection
 
+.pushsection .text.__asm_flush_l3_dcache, "ax"
 ENTRY(__asm_flush_l3_dcache)
        mov     x0, #0                  /* return status as success */
        ret
 ENDPROC(__asm_flush_l3_dcache)
        .weak   __asm_flush_l3_dcache
+.popsection
 
+.pushsection .text.__asm_invalidate_l3_icache, "ax"
 ENTRY(__asm_invalidate_l3_icache)
        mov     x0, #0                  /* return status as success */
        ret
 ENDPROC(__asm_invalidate_l3_icache)
        .weak   __asm_invalidate_l3_icache
+.popsection
 
 /*
  * void __asm_switch_ttbr(ulong new_ttbr)
  *
  * Safely switches to a new page table.
  */
+.pushsection .text.__asm_switch_ttbr, "ax"
 ENTRY(__asm_switch_ttbr)
        /* x2 = SCTLR (alive throghout the function) */
        switch_el x4, 3f, 2f, 1f
@@ -220,3 +264,4 @@ ENTRY(__asm_switch_ttbr)
 
        ret     x3
 ENDPROC(__asm_switch_ttbr)
+.popsection