board: freescale: ls2080a/ls2088a: Enable PPA

[u-boot] / arch / arm / cpu / armv8 / fsl-layerscape / Kconfig

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index adccdf15eb09ce8ea7dfcfc0a0fc5c4e7b621a0b..0068d3c1fa3f343b24dadddec3d9c470d858dabd 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -49,6 +49,10 @@ config ARCH_LS1046A
 config ARCH_LS2080A
        bool
        select ARMV8_SET_SMPEN
+       select ARM_ERRATA_826974
+       select ARM_ERRATA_828024
+       select ARM_ERRATA_829520
+       select ARM_ERRATA_833471
        select FSL_LSCH3
        select SYS_FSL_DDR
        select SYS_FSL_DDR_LE
@@ -69,6 +73,7 @@ config ARCH_LS2080A
        select SYS_FSL_ERRATUM_A009803
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_A010165
+       select SYS_FSL_ERRATUM_A009203
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
 
@@ -85,6 +90,14 @@ config FSL_LSCH3
        select SYS_FSL_SRDS_1
        select SYS_HAS_SERDES
 
+config FSL_MC_ENET
+       bool "Management Complex network"
+       depends on ARCH_LS2080A
+       default y
+       select RESV_RAM
+       help
+         Enable Management Complex (MC) network
+
 menu "Layerscape architecture"
        depends on FSL_LSCH2 || FSL_LSCH3
 
@@ -136,6 +149,7 @@ config SYS_LS_PPA_FW_ADDR
        hex "Address of PPA firmware loading from"
        depends on FSL_LS_PPA
        default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
+       default 0x580a00000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
        default 0x60500000 if SYS_LS_PPA_FW_IN_XIP
        help
          If the PPA firmware locate at XIP flash, such as NOR or
@@ -273,6 +287,16 @@ config SYS_FSL_SDHC_CLK_DIV
          clock, in another word SDHC_clk = Platform_clk / this_divider.
 endmenu
 
+config RESV_RAM
+       bool
+       help
+         Reserve memory from the top, tracked by gd->arch.resv_ram. This
+         reserved RAM can be used by special driver that resides in memory
+         after U-Boot exits. It's up to implementation to allocate and allow
+         access to this reserved memory. For example, the reserved RAM can
+         be at the high end of physical memory. The reserve RAM may be
+         excluded from memory bank(s) passed to OS, or marked as reserved.
+
 config SYS_FSL_ERRATUM_A008336
        bool
 
@@ -285,6 +309,9 @@ config SYS_FSL_ERRATUM_A008585
 config SYS_FSL_ERRATUM_A008850
        bool
 
+config SYS_FSL_ERRATUM_A009203
+       bool
+
 config SYS_FSL_ERRATUM_A009635
        bool
 
@@ -293,3 +320,11 @@ config SYS_FSL_ERRATUM_A009660
 
 config SYS_FSL_ERRATUM_A009929
        bool
+
+config SYS_MC_RSV_MEM_ALIGN
+       hex "Management Complex reserved memory alignment"
+       depends on RESV_RAM
+       default 0x20000000
+       help
+         Reserved memory needs to be aligned for MC to use. Default value
+         is 512MB.