ARMv8/fsl-layerscape: Enable data coherency between cores in cluster

[u-boot] / arch / arm / cpu / armv8 / fsl-layerscape / Kconfig

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 17b470dbd4ec01d852fe6005ff858023e699b56a..7572f19239fed55ecd93e356868bf95b57a38648 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -1,5 +1,6 @@
 config ARCH_LS1012A
        bool
+       select ARMV8_SET_SMPEN
        select FSL_LSCH2
        select SYS_FSL_DDR_BE
        select SYS_FSL_MMDC
@@ -7,36 +8,66 @@ config ARCH_LS1012A
 
 config ARCH_LS1043A
        bool
+       select ARMV8_SET_SMPEN
        select FSL_LSCH2
+       select SYS_FSL_DDR
        select SYS_FSL_DDR_BE
        select SYS_FSL_DDR_VER_50
+       select SYS_FSL_ERRATUM_A008850
+       select SYS_FSL_ERRATUM_A009660
+       select SYS_FSL_ERRATUM_A009663
+       select SYS_FSL_ERRATUM_A009929
+       select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_A010315
        select SYS_FSL_ERRATUM_A010539
+       select SYS_FSL_HAS_DDR3
+       select SYS_FSL_HAS_DDR4
 
 config ARCH_LS1046A
        bool
+       select ARMV8_SET_SMPEN
        select FSL_LSCH2
+       select SYS_FSL_DDR
        select SYS_FSL_DDR_BE
-       select SYS_FSL_DDR4
        select SYS_FSL_DDR_VER_50
+       select SYS_FSL_ERRATUM_A008511
+       select SYS_FSL_ERRATUM_A009801
+       select SYS_FSL_ERRATUM_A009803
+       select SYS_FSL_ERRATUM_A009942
+       select SYS_FSL_ERRATUM_A010165
        select SYS_FSL_ERRATUM_A010539
+       select SYS_FSL_HAS_DDR4
        select SYS_FSL_SRDS_2
 
 config ARCH_LS2080A
        bool
+       select ARMV8_SET_SMPEN
        select FSL_LSCH3
-       select SYS_FSL_DDR4
+       select SYS_FSL_DDR
        select SYS_FSL_DDR_LE
        select SYS_FSL_DDR_VER_50
        select SYS_FSL_HAS_DP_DDR
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_HAS_DDR4
        select SYS_FSL_SEC_COMPAT_5
+       select SYS_FSL_SEC_LE
        select SYS_FSL_SRDS_2
+       select SYS_FSL_ERRATUM_A008336
+       select SYS_FSL_ERRATUM_A008511
+       select SYS_FSL_ERRATUM_A008514
+       select SYS_FSL_ERRATUM_A008585
+       select SYS_FSL_ERRATUM_A009635
+       select SYS_FSL_ERRATUM_A009663
+       select SYS_FSL_ERRATUM_A009801
+       select SYS_FSL_ERRATUM_A009803
+       select SYS_FSL_ERRATUM_A009942
+       select SYS_FSL_ERRATUM_A010165
 
 config FSL_LSCH2
        bool
        select SYS_FSL_HAS_SEC
        select SYS_FSL_SEC_COMPAT_5
+       select SYS_FSL_SEC_BE
        select SYS_FSL_SRDS_1
        select SYS_HAS_SERDES
 
@@ -48,6 +79,17 @@ config FSL_LSCH3
 menu "Layerscape architecture"
        depends on FSL_LSCH2 || FSL_LSCH3
 
+config FSL_PCIE_COMPAT
+       string "PCIe compatible of Kernel DT"
+       depends on PCIE_LAYERSCAPE
+       default "fsl,ls1012a-pcie" if ARCH_LS1012A
+       default "fsl,ls1043a-pcie" if ARCH_LS1043A
+       default "fsl,ls1046a-pcie" if ARCH_LS1046A
+       default "fsl,ls2080a-pcie" if ARCH_LS2080A
+       help
+         This compatible is used to find pci controller node in Kernel DT
+         to complete fixup.
+
 menu "Layerscape PPA"
 config FSL_LS_PPA
        bool "FSL Layerscape PPA firmware support"
@@ -69,9 +111,6 @@ config FSL_PPA_ARMV8_PSCI
          implemented under the common ARMv8 PSCI framework.
 endmenu
 
-config SYS_FSL_MMDC
-       bool
-
 config SYS_FSL_ERRATUM_A010315
        bool "Workaround for PCIe erratum A010315"
 
@@ -91,11 +130,6 @@ config MAX_CPUS
          cores, count the reserved ports. This will allocate enough memory
          in spin table to properly handle all cores.
 
-config NUM_DDR_CONTROLLERS
-       int "Maximum DDR controllers"
-       default 3 if ARCH_LS2080A
-       default 1
-
 config SECURE_BOOT
        bool
        help
@@ -127,49 +161,25 @@ config SYS_FSL_SRDS_2
 config SYS_HAS_SERDES
        bool
 
-config SYS_FSL_DDR
-       bool "Freescale DDR driver"
-       help
-         Select Freescale General DDR driver, shared between most Freescale
-         PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
-         based Layerscape SoCs (such as ls2080a).
+endmenu
 
-config SYS_FSL_DDR_BE
+config SYS_FSL_ERRATUM_A008336
        bool
-       help
-         Access DDR registers in big-endian.
 
-config SYS_FSL_DDR_LE
+config SYS_FSL_ERRATUM_A008514
        bool
-       help
-         Access DDR registers in little-endian.
-
-config SYS_FSL_DDR_VER
-       int
-       default 50 if SYS_FSL_DDR_VER_50
 
-config SYS_FSL_DDR_VER_50
+config SYS_FSL_ERRATUM_A008585
        bool
 
-config SYS_FSL_DDRC_ARM_GEN3
+config SYS_FSL_ERRATUM_A008850
        bool
 
-config SYS_FSL_DDRC_GEN4
+config SYS_FSL_ERRATUM_A009635
        bool
 
-config SYS_FSL_DDR3
-       bool "Freescale DDR3 controller"
-       depends on !SYS_FSL_DDR4
-       select SYS_FSL_DDR
-       select SYS_FSL_DDRC_ARM_GEN3
-       help
-         Enable Freescale DDR3 controller on ARM-based SoCs.
-
-config SYS_FSL_DDR4
-       bool "Freescale DDR4 controller"
-       select SYS_FSL_DDR
-       select SYS_FSL_DDRC_GEN4
-       help
-         Enable Freescale DDR4 controller.
+config SYS_FSL_ERRATUM_A009660
+       bool
 
-endmenu
+config SYS_FSL_ERRATUM_A009929
+       bool