config ARCH_LS1012A
bool
+ select ARMV8_SET_SMPEN
select FSL_LSCH2
select SYS_FSL_DDR_BE
select SYS_FSL_MMDC
config ARCH_LS1043A
bool
+ select ARMV8_SET_SMPEN
select FSL_LSCH2
select SYS_FSL_DDR
select SYS_FSL_DDR_BE
config ARCH_LS1046A
bool
+ select ARMV8_SET_SMPEN
select FSL_LSCH2
select SYS_FSL_DDR
select SYS_FSL_DDR_BE
config ARCH_LS2080A
bool
+ select ARMV8_SET_SMPEN
select FSL_LSCH3
select SYS_FSL_DDR
select SYS_FSL_DDR_LE
menu "Layerscape architecture"
depends on FSL_LSCH2 || FSL_LSCH3
+config FSL_PCIE_COMPAT
+ string "PCIe compatible of Kernel DT"
+ depends on PCIE_LAYERSCAPE
+ default "fsl,ls1012a-pcie" if ARCH_LS1012A
+ default "fsl,ls1043a-pcie" if ARCH_LS1043A
+ default "fsl,ls1046a-pcie" if ARCH_LS1046A
+ default "fsl,ls2080a-pcie" if ARCH_LS2080A
+ help
+ This compatible is used to find pci controller node in Kernel DT
+ to complete fixup.
+
menu "Layerscape PPA"
config FSL_LS_PPA
bool "FSL Layerscape PPA firmware support"
cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.
-config NUM_DDR_CONTROLLERS
- int "Maximum DDR controllers"
- default 3 if ARCH_LS2080A
- default 1
-
config SECURE_BOOT
bool
help