ARMv8/fsl-layerscape: Enable data coherency between cores in cluster

[u-boot] / arch / arm / cpu / armv8 / fsl-layerscape / Kconfig

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index bee7d1537cb495e3da4118c39998f623e2bf3cce..7572f19239fed55ecd93e356868bf95b57a38648 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -1,5 +1,6 @@
 config ARCH_LS1012A
        bool
+       select ARMV8_SET_SMPEN
        select FSL_LSCH2
        select SYS_FSL_DDR_BE
        select SYS_FSL_MMDC
@@ -7,10 +8,16 @@ config ARCH_LS1012A
 
 config ARCH_LS1043A
        bool
+       select ARMV8_SET_SMPEN
        select FSL_LSCH2
        select SYS_FSL_DDR
        select SYS_FSL_DDR_BE
        select SYS_FSL_DDR_VER_50
+       select SYS_FSL_ERRATUM_A008850
+       select SYS_FSL_ERRATUM_A009660
+       select SYS_FSL_ERRATUM_A009663
+       select SYS_FSL_ERRATUM_A009929
+       select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_A010315
        select SYS_FSL_ERRATUM_A010539
        select SYS_FSL_HAS_DDR3
@@ -18,16 +25,23 @@ config ARCH_LS1043A
 
 config ARCH_LS1046A
        bool
+       select ARMV8_SET_SMPEN
        select FSL_LSCH2
        select SYS_FSL_DDR
        select SYS_FSL_DDR_BE
        select SYS_FSL_DDR_VER_50
+       select SYS_FSL_ERRATUM_A008511
+       select SYS_FSL_ERRATUM_A009801
+       select SYS_FSL_ERRATUM_A009803
+       select SYS_FSL_ERRATUM_A009942
+       select SYS_FSL_ERRATUM_A010165
        select SYS_FSL_ERRATUM_A010539
        select SYS_FSL_HAS_DDR4
        select SYS_FSL_SRDS_2
 
 config ARCH_LS2080A
        bool
+       select ARMV8_SET_SMPEN
        select FSL_LSCH3
        select SYS_FSL_DDR
        select SYS_FSL_DDR_LE
@@ -38,6 +52,16 @@ config ARCH_LS2080A
        select SYS_FSL_SEC_COMPAT_5
        select SYS_FSL_SEC_LE
        select SYS_FSL_SRDS_2
+       select SYS_FSL_ERRATUM_A008336
+       select SYS_FSL_ERRATUM_A008511
+       select SYS_FSL_ERRATUM_A008514
+       select SYS_FSL_ERRATUM_A008585
+       select SYS_FSL_ERRATUM_A009635
+       select SYS_FSL_ERRATUM_A009663
+       select SYS_FSL_ERRATUM_A009801
+       select SYS_FSL_ERRATUM_A009803
+       select SYS_FSL_ERRATUM_A009942
+       select SYS_FSL_ERRATUM_A010165
 
 config FSL_LSCH2
        bool
@@ -55,6 +79,17 @@ config FSL_LSCH3
 menu "Layerscape architecture"
        depends on FSL_LSCH2 || FSL_LSCH3
 
+config FSL_PCIE_COMPAT
+       string "PCIe compatible of Kernel DT"
+       depends on PCIE_LAYERSCAPE
+       default "fsl,ls1012a-pcie" if ARCH_LS1012A
+       default "fsl,ls1043a-pcie" if ARCH_LS1043A
+       default "fsl,ls1046a-pcie" if ARCH_LS1046A
+       default "fsl,ls2080a-pcie" if ARCH_LS2080A
+       help
+         This compatible is used to find pci controller node in Kernel DT
+         to complete fixup.
+
 menu "Layerscape PPA"
 config FSL_LS_PPA
        bool "FSL Layerscape PPA firmware support"
@@ -95,11 +130,6 @@ config MAX_CPUS
          cores, count the reserved ports. This will allocate enough memory
          in spin table to properly handle all cores.
 
-config NUM_DDR_CONTROLLERS
-       int "Maximum DDR controllers"
-       default 3 if ARCH_LS2080A
-       default 1
-
 config SECURE_BOOT
        bool
        help
@@ -132,3 +162,24 @@ config SYS_HAS_SERDES
        bool
 
 endmenu
+
+config SYS_FSL_ERRATUM_A008336
+       bool
+
+config SYS_FSL_ERRATUM_A008514
+       bool
+
+config SYS_FSL_ERRATUM_A008585
+       bool
+
+config SYS_FSL_ERRATUM_A008850
+       bool
+
+config SYS_FSL_ERRATUM_A009635
+       bool
+
+config SYS_FSL_ERRATUM_A009660
+       bool
+
+config SYS_FSL_ERRATUM_A009929
+       bool