ARMv8/fsl-layerscape: Enable data coherency between cores in cluster

[u-boot] / arch / arm / cpu / armv8 / fsl-layerscape / Kconfig

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index c6cf7749ada48a8bf2fe484ff17c65dfaeb5679b..7572f19239fed55ecd93e356868bf95b57a38648 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -1,35 +1,115 @@
 config ARCH_LS1012A
        bool
+       select ARMV8_SET_SMPEN
        select FSL_LSCH2
+       select SYS_FSL_DDR_BE
        select SYS_FSL_MMDC
        select SYS_FSL_ERRATUM_A010315
 
 config ARCH_LS1043A
        bool
+       select ARMV8_SET_SMPEN
        select FSL_LSCH2
+       select SYS_FSL_DDR
+       select SYS_FSL_DDR_BE
+       select SYS_FSL_DDR_VER_50
+       select SYS_FSL_ERRATUM_A008850
+       select SYS_FSL_ERRATUM_A009660
+       select SYS_FSL_ERRATUM_A009663
+       select SYS_FSL_ERRATUM_A009929
+       select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_A010315
        select SYS_FSL_ERRATUM_A010539
+       select SYS_FSL_HAS_DDR3
+       select SYS_FSL_HAS_DDR4
 
 config ARCH_LS1046A
        bool
+       select ARMV8_SET_SMPEN
        select FSL_LSCH2
+       select SYS_FSL_DDR
+       select SYS_FSL_DDR_BE
+       select SYS_FSL_DDR_VER_50
+       select SYS_FSL_ERRATUM_A008511
+       select SYS_FSL_ERRATUM_A009801
+       select SYS_FSL_ERRATUM_A009803
+       select SYS_FSL_ERRATUM_A009942
+       select SYS_FSL_ERRATUM_A010165
        select SYS_FSL_ERRATUM_A010539
+       select SYS_FSL_HAS_DDR4
+       select SYS_FSL_SRDS_2
 
 config ARCH_LS2080A
        bool
+       select ARMV8_SET_SMPEN
        select FSL_LSCH3
+       select SYS_FSL_DDR
+       select SYS_FSL_DDR_LE
+       select SYS_FSL_DDR_VER_50
+       select SYS_FSL_HAS_DP_DDR
+       select SYS_FSL_HAS_SEC
+       select SYS_FSL_HAS_DDR4
+       select SYS_FSL_SEC_COMPAT_5
+       select SYS_FSL_SEC_LE
+       select SYS_FSL_SRDS_2
+       select SYS_FSL_ERRATUM_A008336
+       select SYS_FSL_ERRATUM_A008511
+       select SYS_FSL_ERRATUM_A008514
+       select SYS_FSL_ERRATUM_A008585
+       select SYS_FSL_ERRATUM_A009635
+       select SYS_FSL_ERRATUM_A009663
+       select SYS_FSL_ERRATUM_A009801
+       select SYS_FSL_ERRATUM_A009803
+       select SYS_FSL_ERRATUM_A009942
+       select SYS_FSL_ERRATUM_A010165
 
 config FSL_LSCH2
        bool
+       select SYS_FSL_HAS_SEC
+       select SYS_FSL_SEC_COMPAT_5
+       select SYS_FSL_SEC_BE
+       select SYS_FSL_SRDS_1
+       select SYS_HAS_SERDES
 
 config FSL_LSCH3
        bool
+       select SYS_FSL_SRDS_1
+       select SYS_HAS_SERDES
 
 menu "Layerscape architecture"
        depends on FSL_LSCH2 || FSL_LSCH3
 
-config SYS_FSL_MMDC
-       bool
+config FSL_PCIE_COMPAT
+       string "PCIe compatible of Kernel DT"
+       depends on PCIE_LAYERSCAPE
+       default "fsl,ls1012a-pcie" if ARCH_LS1012A
+       default "fsl,ls1043a-pcie" if ARCH_LS1043A
+       default "fsl,ls1046a-pcie" if ARCH_LS1046A
+       default "fsl,ls2080a-pcie" if ARCH_LS2080A
+       help
+         This compatible is used to find pci controller node in Kernel DT
+         to complete fixup.
+
+menu "Layerscape PPA"
+config FSL_LS_PPA
+       bool "FSL Layerscape PPA firmware support"
+       depends on !ARMV8_PSCI
+       depends on ARCH_LS1043A || ARCH_LS1046A
+       select FSL_PPA_ARMV8_PSCI
+       help
+         The FSL Primary Protected Application (PPA) is a software component
+         which is loaded during boot stage, and then remains resident in RAM
+         and runs in the TrustZone after boot.
+         Say y to enable it.
+
+config FSL_PPA_ARMV8_PSCI
+       bool "PSCI implementation in PPA firmware"
+       depends on FSL_LS_PPA
+       help
+         This config enables the ARMv8 PSCI implementation in PPA firmware.
+         This is a private PSCI implementation and different from those
+         implemented under the common ARMv8 PSCI framework.
+endmenu
 
 config SYS_FSL_ERRATUM_A010315
        bool "Workaround for PCIe erratum A010315"
@@ -50,6 +130,18 @@ config MAX_CPUS
          cores, count the reserved ports. This will allocate enough memory
          in spin table to properly handle all cores.
 
+config SECURE_BOOT
+       bool
+       help
+               Enable Freescale Secure Boot feature
+
+config QSPI_AHB_INIT
+       bool "Init the QSPI AHB bus"
+       help
+         The default setting for QSPI AHB bus just support 3bytes addressing.
+         But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
+         bus for those flashes to support the full QSPI flash size.
+
 config SYS_FSL_IFC_BANK_COUNT
        int "Maximum banks of Integrated flash controller"
        depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
@@ -57,4 +149,37 @@ config SYS_FSL_IFC_BANK_COUNT
        default 4 if ARCH_LS1046A
        default 8 if ARCH_LS2080A
 
+config SYS_FSL_HAS_DP_DDR
+       bool
+
+config SYS_FSL_SRDS_1
+       bool
+
+config SYS_FSL_SRDS_2
+       bool
+
+config SYS_HAS_SERDES
+       bool
+
 endmenu
+
+config SYS_FSL_ERRATUM_A008336
+       bool
+
+config SYS_FSL_ERRATUM_A008514
+       bool
+
+config SYS_FSL_ERRATUM_A008585
+       bool
+
+config SYS_FSL_ERRATUM_A008850
+       bool
+
+config SYS_FSL_ERRATUM_A009635
+       bool
+
+config SYS_FSL_ERRATUM_A009660
+       bool
+
+config SYS_FSL_ERRATUM_A009929
+       bool