armv8: Remove dependency of SERDES for LSCH2 and LSCH3

[u-boot] / arch / arm / cpu / armv8 / fsl-layerscape / Kconfig

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 6c03dfb1d58cf015dbb05c8a2618b1aa9fc03798..7b59dc9a7c8b4e94bca89678b94dbea160258a2b 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -1,7 +1,10 @@
 config ARCH_LS1012A
        bool
        select ARMV8_SET_SMPEN
+       select ARM_ERRATA_855873
        select FSL_LSCH2
+       select SYS_FSL_SRDS_1
+       select SYS_HAS_SERDES
        select SYS_FSL_DDR_BE
        select SYS_FSL_MMDC
        select SYS_FSL_ERRATUM_A010315
@@ -16,7 +19,10 @@ config ARCH_LS1012A
 config ARCH_LS1043A
        bool
        select ARMV8_SET_SMPEN
+       select ARM_ERRATA_855873
        select FSL_LSCH2
+       select SYS_FSL_SRDS_1
+       select SYS_HAS_SERDES
        select SYS_FSL_DDR
        select SYS_FSL_DDR_BE
        select SYS_FSL_DDR_VER_50
@@ -43,6 +49,8 @@ config ARCH_LS1046A
        bool
        select ARMV8_SET_SMPEN
        select FSL_LSCH2
+       select SYS_FSL_SRDS_1
+       select SYS_HAS_SERDES
        select SYS_FSL_DDR
        select SYS_FSL_DDR_BE
        select SYS_FSL_DDR_VER_50
@@ -68,7 +76,10 @@ config ARCH_LS1046A
 config ARCH_LS1088A
        bool
        select ARMV8_SET_SMPEN
+       select ARM_ERRATA_855873
        select FSL_LSCH3
+       select SYS_FSL_SRDS_1
+       select SYS_HAS_SERDES
        select SYS_FSL_DDR
        select SYS_FSL_DDR_LE
        select SYS_FSL_DDR_VER_50
@@ -102,6 +113,8 @@ config ARCH_LS2080A
        select ARM_ERRATA_829520
        select ARM_ERRATA_833471
        select FSL_LSCH3
+       select SYS_FSL_SRDS_1
+       select SYS_HAS_SERDES
        select SYS_FSL_DDR
        select SYS_FSL_DDR_LE
        select SYS_FSL_DDR_VER_50
@@ -139,13 +152,9 @@ config FSL_LSCH2
        select SYS_FSL_HAS_SEC
        select SYS_FSL_SEC_COMPAT_5
        select SYS_FSL_SEC_BE
-       select SYS_FSL_SRDS_1
-       select SYS_HAS_SERDES
 
 config FSL_LSCH3
        bool
-       select SYS_FSL_SRDS_1
-       select SYS_HAS_SERDES
 
 config FSL_MC_ENET
        bool "Management Complex network"
@@ -493,8 +502,7 @@ config SYS_FSL_HAS_RGMII
 config SYS_MC_RSV_MEM_ALIGN
        hex "Management Complex reserved memory alignment"
        depends on RESV_RAM
-       default 0x20000000 if ARCH_LS2080A
-       default 0x70000000 if ARCH_LS1088A
+       default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A
        help
          Reserved memory needs to be aligned for MC to use. Default value
          is 512MB.