distro: use imply to enable DISTRO_DEFAULTS as SoC default

[u-boot] / arch / arm / cpu / armv8 / fsl-layerscape / Kconfig

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 4866550c0dcaa9ddf97c56e3b9971379179ef622..7edc06d20263a1970d78b7684e07a24f92a02e4e 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -1,7 +1,10 @@
 config ARCH_LS1012A
        bool
        select ARMV8_SET_SMPEN
+       select ARM_ERRATA_855873
        select FSL_LSCH2
+       select SYS_FSL_SRDS_1
+       select SYS_HAS_SERDES
        select SYS_FSL_DDR_BE
        select SYS_FSL_MMDC
        select SYS_FSL_ERRATUM_A010315
@@ -11,11 +14,18 @@ config ARCH_LS1012A
        select SYS_FSL_ERRATUM_A009008
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
+       select SYS_I2C_MXC
+       select SYS_I2C_MXC_I2C1
+       select SYS_I2C_MXC_I2C2
+       imply PANIC_HANG
 
 config ARCH_LS1043A
        bool
        select ARMV8_SET_SMPEN
+       select ARM_ERRATA_855873
        select FSL_LSCH2
+       select SYS_FSL_SRDS_1
+       select SYS_HAS_SERDES
        select SYS_FSL_DDR
        select SYS_FSL_DDR_BE
        select SYS_FSL_DDR_VER_50
@@ -34,13 +44,21 @@ config ARCH_LS1043A
        select SYS_FSL_HAS_DDR4
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
+       select SYS_I2C_MXC
+       select SYS_I2C_MXC_I2C1
+       select SYS_I2C_MXC_I2C2
+       select SYS_I2C_MXC_I2C3
+       select SYS_I2C_MXC_I2C4
        imply SCSI
+       imply SCSI_AHCI
        imply CMD_PCI
 
 config ARCH_LS1046A
        bool
        select ARMV8_SET_SMPEN
        select FSL_LSCH2
+       select SYS_FSL_SRDS_1
+       select SYS_HAS_SERDES
        select SYS_FSL_DDR
        select SYS_FSL_DDR_BE
        select SYS_FSL_DDR_VER_50
@@ -60,12 +78,21 @@ config ARCH_LS1046A
        select SYS_FSL_SRDS_2
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
+       select SYS_I2C_MXC
+       select SYS_I2C_MXC_I2C1
+       select SYS_I2C_MXC_I2C2
+       select SYS_I2C_MXC_I2C3
+       select SYS_I2C_MXC_I2C4
        imply SCSI
+       imply SCSI_AHCI
 
 config ARCH_LS1088A
        bool
        select ARMV8_SET_SMPEN
+       select ARM_ERRATA_855873
        select FSL_LSCH3
+       select SYS_FSL_SRDS_1
+       select SYS_HAS_SERDES
        select SYS_FSL_DDR
        select SYS_FSL_DDR_LE
        select SYS_FSL_DDR_VER_50
@@ -88,7 +115,13 @@ config ARCH_LS1088A
        select FSL_TZASC_1
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
+       select SYS_I2C_MXC
+       select SYS_I2C_MXC_I2C1
+       select SYS_I2C_MXC_I2C2
+       select SYS_I2C_MXC_I2C3
+       select SYS_I2C_MXC_I2C4
        imply SCSI
+       imply PANIC_HANG
 
 config ARCH_LS2080A
        bool
@@ -98,6 +131,8 @@ config ARCH_LS2080A
        select ARM_ERRATA_829520
        select ARM_ERRATA_833471
        select FSL_LSCH3
+       select SYS_FSL_SRDS_1
+       select SYS_HAS_SERDES
        select SYS_FSL_DDR
        select SYS_FSL_DDR_LE
        select SYS_FSL_DDR_VER_50
@@ -127,6 +162,13 @@ config ARCH_LS2080A
        select SYS_FSL_ERRATUM_A009203
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
+       select SYS_I2C_MXC
+       select SYS_I2C_MXC_I2C1
+       select SYS_I2C_MXC_I2C2
+       select SYS_I2C_MXC_I2C3
+       select SYS_I2C_MXC_I2C4
+       imply DISTRO_DEFAULTS
+       imply PANIC_HANG
 
 config FSL_LSCH2
        bool
@@ -134,13 +176,9 @@ config FSL_LSCH2
        select SYS_FSL_HAS_SEC
        select SYS_FSL_SEC_COMPAT_5
        select SYS_FSL_SEC_BE
-       select SYS_FSL_SRDS_1
-       select SYS_HAS_SERDES
 
 config FSL_LSCH3
        bool
-       select SYS_FSL_SRDS_1
-       select SYS_HAS_SERDES
 
 config FSL_MC_ENET
        bool "Management Complex network"
@@ -248,6 +286,7 @@ config SYS_LS_PPA_ESBC_ADDR
        default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
        default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
        default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
+       default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A
        default 0x680000 if SYS_LS_PPA_FW_IN_MMC
        default 0x680000 if SYS_LS_PPA_FW_IN_NAND
        help
@@ -487,8 +526,7 @@ config SYS_FSL_HAS_RGMII
 config SYS_MC_RSV_MEM_ALIGN
        hex "Management Complex reserved memory alignment"
        depends on RESV_RAM
-       default 0x20000000 if ARCH_LS2080A
-       default 0x70000000 if ARCH_LS1088A
+       default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A
        help
          Reserved memory needs to be aligned for MC to use. Default value
          is 512MB.