armv8: fsl-layerscape: Move SECURE_BOOT to Kconfig

[u-boot] / arch / arm / cpu / armv8 / fsl-layerscape / Kconfig

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 28589aea8f1cb5b3f274ac5f8cb0b387a4c8e8c1..ed1c4eeb03c07d249b0c358f40163c407401cfd1 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -1,24 +1,33 @@
 config ARCH_LS1012A
        bool
        select FSL_LSCH2
+       select SYS_FSL_DDR_BE
        select SYS_FSL_MMDC
        select SYS_FSL_ERRATUM_A010315
 
 config ARCH_LS1043A
        bool
        select FSL_LSCH2
+       select SYS_FSL_DDR_BE
+       select SYS_FSL_DDR_VER_50
        select SYS_FSL_ERRATUM_A010315
        select SYS_FSL_ERRATUM_A010539
 
 config ARCH_LS1046A
        bool
        select FSL_LSCH2
+       select SYS_FSL_DDR_BE
+       select SYS_FSL_DDR4
+       select SYS_FSL_DDR_VER_50
        select SYS_FSL_ERRATUM_A010539
        select SYS_FSL_SRDS_2
 
 config ARCH_LS2080A
        bool
        select FSL_LSCH3
+       select SYS_FSL_DDR4
+       select SYS_FSL_DDR_LE
+       select SYS_FSL_DDR_VER_50
        select SYS_FSL_HAS_DP_DDR
        select SYS_FSL_SRDS_2
 
@@ -62,6 +71,11 @@ config NUM_DDR_CONTROLLERS
        default 3 if ARCH_LS2080A
        default 1
 
+config SECURE_BOOT
+       bool
+       help
+               Enable Freescale Secure Boot feature
+
 config SYS_FSL_IFC_BANK_COUNT
        int "Maximum banks of Integrated flash controller"
        depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
@@ -81,4 +95,49 @@ config SYS_FSL_SRDS_2
 config SYS_HAS_SERDES
        bool
 
+config SYS_FSL_DDR
+       bool "Freescale DDR driver"
+       help
+         Select Freescale General DDR driver, shared between most Freescale
+         PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
+         based Layerscape SoCs (such as ls2080a).
+
+config SYS_FSL_DDR_BE
+       bool
+       help
+         Access DDR registers in big-endian.
+
+config SYS_FSL_DDR_LE
+       bool
+       help
+         Access DDR registers in little-endian.
+
+config SYS_FSL_DDR_VER
+       int
+       default 50 if SYS_FSL_DDR_VER_50
+
+config SYS_FSL_DDR_VER_50
+       bool
+
+config SYS_FSL_DDRC_ARM_GEN3
+       bool
+
+config SYS_FSL_DDRC_GEN4
+       bool
+
+config SYS_FSL_DDR3
+       bool "Freescale DDR3 controller"
+       depends on !SYS_FSL_DDR4
+       select SYS_FSL_DDR
+       select SYS_FSL_DDRC_ARM_GEN3
+       help
+         Enable Freescale DDR3 controller on ARM-based SoCs.
+
+config SYS_FSL_DDR4
+       bool "Freescale DDR4 controller"
+       select SYS_FSL_DDR
+       select SYS_FSL_DDRC_GEN4
+       help
+         Enable Freescale DDR4 controller.
+
 endmenu