Merge git://git.denx.de/u-boot-fsl-qoriq

[u-boot] / arch / arm / cpu / armv8 / fsl-layerscape / cpu.c

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 7404bd932a184c043cad8bb10611113ec0cfa0d9..8062106e3e90fad3df513ab7e4a4e26fbdab2115 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -396,9 +396,6 @@ static inline void final_mmu_setup(void)
        flush_dcache_range((ulong)level0_table,
                           (ulong)level0_table + gd->arch.tlb_size);
 
-#ifdef CONFIG_SYS_DPAA_FMAN
-       flush_dcache_all();
-#endif
        /* point TTBR to the new table */
        set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR_FINAL,
                          MEMORY_ATTRIBUTES);
@@ -410,6 +407,11 @@ static inline void final_mmu_setup(void)
         */
 }
 
+u64 get_page_table_size(void)
+{
+       return 0x10000;
+}
+
 int arch_cpu_init(void)
 {
        icache_enable();
@@ -526,6 +528,13 @@ u32 fsl_qoriq_core_to_type(unsigned int core)
        return -1;      /* cannot identify the cluster */
 }
 
+uint get_svr(void)
+{
+       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+       return gur_in32(&gur->svr);
+}
+
 #ifdef CONFIG_DISPLAY_CPUINFO
 int print_cpuinfo(void)
 {
@@ -533,12 +542,12 @@ int print_cpuinfo(void)
        struct sys_info sysinfo;
        char buf[32];
        unsigned int i, core;
-       u32 type, rcw;
+       u32 type, rcw, svr = gur_in32(&gur->svr);
 
        puts("SoC: ");
 
        cpu_name(buf);
-       printf(" %s (0x%x)\n", buf, gur_in32(&gur->svr));
+       printf(" %s (0x%x)\n", buf, svr);
        memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
        get_sys_info(&sysinfo);
        puts("Clock Configuration:");
@@ -559,7 +568,10 @@ int print_cpuinfo(void)
        printf("  FMAN:     %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
 #endif
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-       printf("     DP-DDR:   %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2));
+       if (soc_has_dp_ddr()) {
+               printf("     DP-DDR:   %-4s MT/s",
+                      strmhz(buf, sysinfo.freq_ddrbus2));
+       }
 #endif
        puts("\n");
 
@@ -631,6 +643,9 @@ int timer_init(void)
 #ifdef CONFIG_FSL_LSCH3
        u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
 #endif
+#ifdef CONFIG_LS2080A
+       u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
+#endif
 #ifdef COUNTER_FREQUENCY_REAL
        unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
 
@@ -645,6 +660,15 @@ int timer_init(void)
        out_le32(cltbenr, 0xf);
 #endif
 
+#ifdef CONFIG_LS2080A
+       /*
+        * In certain Layerscape SoCs, the clock for each core's
+        * has an enable bit in the PMU Physical Core Time Base Enable
+        * Register (PCTBENR), which allows the watchdog to operate.
+        */
+       setbits_le32(pctbenr, 0xff);
+#endif
+
        /* Enable clock for timer
         * This is a global setting.
         */