DECLARE_GLOBAL_DATA_PTR;
+static struct mm_region layerscape_mem_map[] = {
+ {
+ /* List terminator */
+ 0,
+ }
+};
+struct mm_region *mem_map = layerscape_mem_map;
+
void cpu_name(char *name)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
}
#ifndef CONFIG_SYS_DCACHE_OFF
+static void set_pgtable_section(u64 *page_table, u64 index, u64 section,
+ u64 memory_type, u64 attribute)
+{
+ u64 value;
+
+ value = section | PTE_TYPE_BLOCK | PTE_BLOCK_AF;
+ value |= PMD_ATTRINDX(memory_type);
+ value |= attribute;
+ page_table[index] = value;
+}
+
+static void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr)
+{
+ u64 value;
+
+ value = (u64)table_addr | PTE_TYPE_TABLE;
+ page_table[index] = value;
+}
+
/*
* Set the block entries according to the information of the table.
*/
temp_base -= block_size;
- if ((level_table[index - 1] & PMD_TYPE_MASK) ==
- PMD_TYPE_TABLE) {
+ if ((level_table[index - 1] & PTE_TYPE_MASK) ==
+ PTE_TYPE_TABLE) {
level_table = (u64 *)(level_table[index - 1] &
- ~PMD_TYPE_MASK);
+ ~PTE_TYPE_MASK);
level++;
continue;
} else {
struct table_info table = {};
struct sys_mmu_table ddr_entry = {
0, 0, BLOCK_SIZE_L1, MT_NORMAL,
- PMD_SECT_OUTER_SHARE | PMD_SECT_NS
+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
};
u64 index;
ddr_entry.virt_addr = phys_addr;
ddr_entry.phys_addr = phys_addr;
ddr_entry.size = CONFIG_SYS_MEM_RESERVE_SECURE;
- ddr_entry.attribute = PMD_SECT_OUTER_SHARE;
+ ddr_entry.attribute = PTE_BLOCK_OUTER_SHARE;
ret = find_table(&ddr_entry, &table, level0_table);
if (ret) {
printf("MMU error: could not find secure ddr table\n");
flush_dcache_range((ulong)level0_table,
(ulong)level0_table + gd->arch.tlb_size);
-#ifdef CONFIG_SYS_DPAA_FMAN
- flush_dcache_all();
-#endif
/* point TTBR to the new table */
set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR_FINAL,
MEMORY_ATTRIBUTES);
*/
}
+u64 get_page_table_size(void)
+{
+ return 0x10000;
+}
+
int arch_cpu_init(void)
{
icache_enable();
return -1; /* cannot identify the cluster */
}
+uint get_svr(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+ return gur_in32(&gur->svr);
+}
+
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
struct sys_info sysinfo;
char buf[32];
unsigned int i, core;
- u32 type, rcw;
+ u32 type, rcw, svr = gur_in32(&gur->svr);
puts("SoC: ");
cpu_name(buf);
- printf(" %s (0x%x)\n", buf, gur_in32(&gur->svr));
+ printf(" %s (0x%x)\n", buf, svr);
memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
get_sys_info(&sysinfo);
puts("Clock Configuration:");
printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
#endif
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
- printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2));
+ if (soc_has_dp_ddr()) {
+ printf(" DP-DDR: %-4s MT/s",
+ strmhz(buf, sysinfo.freq_ddrbus2));
+ }
#endif
puts("\n");
#ifdef CONFIG_FSL_LSCH3
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
#endif
+#ifdef CONFIG_LS2080A
+ u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
+#endif
#ifdef COUNTER_FREQUENCY_REAL
unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
out_le32(cltbenr, 0xf);
#endif
+#ifdef CONFIG_LS2080A
+ /*
+ * In certain Layerscape SoCs, the clock for each core's
+ * has an enable bit in the PMU Physical Core Time Base Enable
+ * Register (PCTBENR), which allows the watchdog to operate.
+ */
+ setbits_le32(pctbenr, 0xff);
+#endif
+
/* Enable clock for timer
* This is a global setting.
*/
val |= 0x02;
scfg_out32(rstcr, val);
}
+
+phys_size_t board_reserve_ram_top(phys_size_t ram_size)
+{
+ phys_size_t ram_top = ram_size;
+
+#ifdef CONFIG_SYS_MEM_TOP_HIDE
+#error CONFIG_SYS_MEM_TOP_HIDE not to be used together with this function
+#endif
+/* Carve the Debug Server private DRAM block from the end of DRAM */
+#ifdef CONFIG_FSL_DEBUG_SERVER
+ ram_top -= debug_server_get_dram_block_size();
+#endif
+
+/* Carve the MC private DRAM block from the end of DRAM */
+#ifdef CONFIG_FSL_MC_ENET
+ ram_top -= mc_get_dram_block_size();
+ ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
+#endif
+
+ return ram_top;
+}