Merge git://git.denx.de/u-boot-fdt

[u-boot] / arch / arm / cpu / armv8 / fsl-layerscape / cpu.c

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index e12b77355068a195ab461b5ef2ea19aade1b4317..d6ee54642d214cb1445adab7965e09f6110c12b5 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/system.h>
 #include <asm/armv8/mmu.h>
 #include <asm/io.h>
@@ -17,8 +17,8 @@
 #ifdef CONFIG_MP
 #include <asm/arch/mp.h>
 #endif
+#include <efi_loader.h>
 #include <fm_eth.h>
-#include <fsl_debug_server.h>
 #include <fsl-mc/fsl_mc.h>
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
@@ -45,6 +45,9 @@ void cpu_name(char *name)
 
                        if (IS_E_PROCESSOR(svr))
                                strcat(name, "E");
+
+                       sprintf(name + strlen(name), " Rev%d.%d",
+                               SVR_MAJ(svr), SVR_MIN(svr));
                        break;
                }
 
@@ -188,7 +191,7 @@ void enable_caches(void)
 }
 #endif
 
-static inline u32 initiator_type(u32 cluster, int init_id)
+u32 initiator_type(u32 cluster, int init_id)
 {
        struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
        u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
@@ -201,6 +204,27 @@ static inline u32 initiator_type(u32 cluster, int init_id)
        return 0;
 }
 
+u32 cpu_pos_mask(void)
+{
+       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+       int i = 0;
+       u32 cluster, type, mask = 0;
+
+       do {
+               int j;
+
+               cluster = gur_in32(&gur->tp_cluster[i].lower);
+               for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+                       type = initiator_type(cluster, j);
+                       if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
+                               mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
+               }
+               i++;
+       } while ((cluster & TP_CLUSTER_EOC) == 0x0);
+
+       return mask;
+}
+
 u32 cpu_mask(void)
 {
        struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -282,12 +306,14 @@ u32 fsl_qoriq_core_to_type(unsigned int core)
        return -1;      /* cannot identify the cluster */
 }
 
+#ifndef CONFIG_FSL_LSCH3
 uint get_svr(void)
 {
        struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 
        return gur_in32(&gur->svr);
 }
+#endif
 
 #ifdef CONFIG_DISPLAY_CPUINFO
 int print_cpuinfo(void)
@@ -407,6 +433,7 @@ int timer_init(void)
 #endif
 #ifdef CONFIG_LS2080A
        u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
+       u32 svr_dev_id;
 #endif
 #ifdef COUNTER_FREQUENCY_REAL
        unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
@@ -429,6 +456,14 @@ int timer_init(void)
         * Register (PCTBENR), which allows the watchdog to operate.
         */
        setbits_le32(pctbenr, 0xff);
+       /*
+        * For LS2080A SoC and its personalities, timer controller
+        * offset is different
+        */
+       svr_dev_id = get_svr() >> 16;
+       if (svr_dev_id == SVR_DEV_LS2080A)
+               cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
+
 #endif
 
        /* Enable clock for timer
@@ -439,9 +474,10 @@ int timer_init(void)
        return 0;
 }
 
-void reset_cpu(ulong addr)
+__efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
+
+void __efi_runtime reset_cpu(ulong addr)
 {
-       u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
        u32 val;
 
        /* Raise RESET_REQ_B */
@@ -450,6 +486,33 @@ void reset_cpu(ulong addr)
        scfg_out32(rstcr, val);
 }
 
+#ifdef CONFIG_EFI_LOADER
+
+void __efi_runtime EFIAPI efi_reset_system(
+                      enum efi_reset_type reset_type,
+                      efi_status_t reset_status,
+                      unsigned long data_size, void *reset_data)
+{
+       switch (reset_type) {
+       case EFI_RESET_COLD:
+       case EFI_RESET_WARM:
+               reset_cpu(0);
+               break;
+       case EFI_RESET_SHUTDOWN:
+               /* Nothing we can do */
+               break;
+       }
+
+       while (1) { }
+}
+
+void efi_reset_system_init(void)
+{
+       efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
+}
+
+#endif
+
 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
 {
        phys_size_t ram_top = ram_size;
@@ -457,10 +520,6 @@ phys_size_t board_reserve_ram_top(phys_size_t ram_size)
 #ifdef CONFIG_SYS_MEM_TOP_HIDE
 #error CONFIG_SYS_MEM_TOP_HIDE not to be used together with this function
 #endif
-/* Carve the Debug Server private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_DEBUG_SERVER
-       ram_top -= debug_server_get_dram_block_size();
-#endif
 
 /* Carve the MC private DRAM block from the end of DRAM */
 #ifdef CONFIG_FSL_MC_ENET