#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/system.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
#ifdef CONFIG_MP
#include <asm/arch/mp.h>
#endif
+#include <efi_loader.h>
#include <fm_eth.h>
-#include <fsl_debug_server.h>
#include <fsl-mc/fsl_mc.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif
+#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
+#include <asm/armv8/sec_firmware.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
if (IS_E_PROCESSOR(svr))
strcat(name, "E");
+
+ sprintf(name + strlen(name), " Rev%d.%d",
+ SVR_MAJ(svr), SVR_MIN(svr));
break;
}
set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
MEMORY_ATTRIBUTES);
/*
- * MMU is already enabled, just need to invalidate TLB to load the
+ * EL3 MMU is already enabled, just need to invalidate TLB to load the
* new table. The new table is compatible with the current table, if
* MMU somehow walks through the new table before invalidation TLB,
* it still works. So we don't need to turn off MMU here.
+ * When EL2 MMU table is created by calling this function, MMU needs
+ * to be enabled.
*/
+ set_sctlr(get_sctlr() | CR_M);
}
u64 get_page_table_size(void)
return 0;
}
+void mmu_setup(void)
+{
+ final_mmu_setup();
+}
+
/*
- * This function is called from lib/board.c.
- * It recreates MMU table in main memory. MMU and d-cache are enabled earlier.
- * There is no need to disable d-cache for this operation.
+ * This function is called from common/board_r.c.
+ * It recreates MMU table in main memory.
*/
void enable_caches(void)
{
- final_mmu_setup();
+ mmu_setup();
__asm_invalidate_tlb_all();
+ icache_enable();
+ dcache_enable();
}
#endif
return 0;
}
+u32 cpu_pos_mask(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ int i = 0;
+ u32 cluster, type, mask = 0;
+
+ do {
+ int j;
+
+ cluster = gur_in32(&gur->tp_cluster[i].lower);
+ for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+ type = initiator_type(cluster, j);
+ if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
+ mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
+ }
+ i++;
+ } while ((cluster & TP_CLUSTER_EOC) == 0x0);
+
+ return mask;
+}
+
u32 cpu_mask(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
return -1; /* cannot identify the cluster */
}
+#ifndef CONFIG_FSL_LSCH3
uint get_svr(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
return gur_in32(&gur->svr);
}
+#endif
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
printf("CPU%d(%s):%-4s MHz ", core,
type == TY_ITYP_VER_A7 ? "A7 " :
(type == TY_ITYP_VER_A53 ? "A53" :
- (type == TY_ITYP_VER_A57 ? "A57" : " ")),
+ (type == TY_ITYP_VER_A57 ? "A57" :
+ (type == TY_ITYP_VER_A72 ? "A72" : " "))),
strmhz(buf, sysinfo.freq_processor[core]));
}
printf("\n Bus: %-4s MHz ",
{
#ifdef CONFIG_MP
int rv = 1;
+ u32 psci_ver = 0xffffffff;
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
#endif
#ifdef CONFIG_MP
- rv = fsl_layerscape_wake_seconday_cores();
- if (rv)
- printf("Did not wake secondary cores\n");
+#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI)
+ /* Check the psci version to determine if the psci is supported */
+ psci_ver = sec_firmware_support_psci_version();
+#endif
+ if (psci_ver == 0xffffffff) {
+ rv = fsl_layerscape_wake_seconday_cores();
+ if (rv)
+ printf("Did not wake secondary cores\n");
+ }
#endif
#ifdef CONFIG_SYS_HAS_SERDES
#endif
#ifdef CONFIG_LS2080A
u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
+ u32 svr_dev_id;
#endif
#ifdef COUNTER_FREQUENCY_REAL
unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
* Register (PCTBENR), which allows the watchdog to operate.
*/
setbits_le32(pctbenr, 0xff);
+ /*
+ * For LS2080A SoC and its personalities, timer controller
+ * offset is different
+ */
+ svr_dev_id = get_svr() >> 16;
+ if (svr_dev_id == SVR_DEV_LS2080A)
+ cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
+
#endif
/* Enable clock for timer
return 0;
}
-void reset_cpu(ulong addr)
+__efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
+
+void __efi_runtime reset_cpu(ulong addr)
{
- u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
u32 val;
/* Raise RESET_REQ_B */
scfg_out32(rstcr, val);
}
+#ifdef CONFIG_EFI_LOADER
+
+void __efi_runtime EFIAPI efi_reset_system(
+ enum efi_reset_type reset_type,
+ efi_status_t reset_status,
+ unsigned long data_size, void *reset_data)
+{
+ switch (reset_type) {
+ case EFI_RESET_COLD:
+ case EFI_RESET_WARM:
+ reset_cpu(0);
+ break;
+ case EFI_RESET_SHUTDOWN:
+ /* Nothing we can do */
+ break;
+ }
+
+ while (1) { }
+}
+
+void efi_reset_system_init(void)
+{
+ efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
+}
+
+#endif
+
phys_size_t board_reserve_ram_top(phys_size_t ram_size)
{
phys_size_t ram_top = ram_size;
#ifdef CONFIG_SYS_MEM_TOP_HIDE
#error CONFIG_SYS_MEM_TOP_HIDE not to be used together with this function
#endif
-/* Carve the Debug Server private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_DEBUG_SERVER
- ram_top -= debug_server_get_dram_block_size();
-#endif
/* Carve the MC private DRAM block from the end of DRAM */
#ifdef CONFIG_FSL_MC_ENET