#include <asm/arch/clock.h>
#include <asm/arch/soc.h>
#include <fsl_ifc.h>
+#include "cpu.h"
DECLARE_GLOBAL_DATA_PTR;
[5] = 2, /* CC2 PPL / 2 */
};
- uint i;
+ uint i, cluster;
uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
sys_info->freq_ddrbus = sysclk;
#endif
-#ifdef CONFIG_LS1012A
+#ifdef CONFIG_ARCH_LS1012A
sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
}
- for (cpu = 0; cpu < CONFIG_MAX_CPUS; cpu++) {
- u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
+ for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
+ cluster = fsl_qoriq_core_to_cluster(cpu);
+ u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
& 0xf;
u32 cplx_pll = core_cplx_pll[c_pll_sel];
freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
}
-#ifdef CONFIG_LS1012A
+#ifdef CONFIG_ARCH_LS1012A
sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
sys_info->freq_ddrbus *= 2;
#endif
case 3:
sys_info->freq_fman[0] = freq_c_pll[0] / 3;
break;
+ case 4:
+ sys_info->freq_fman[0] = freq_c_pll[0] / 4;
+ break;
+ case 5:
+ sys_info->freq_fman[0] = sys_info->freq_systembus;
+ break;
case 6:
sys_info->freq_fman[0] = freq_c_pll[1] / 2;
break;
#ifdef CONFIG_FSL_ESDHC
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
rcw_tmp = in_be32(&gur->rcwsr[15]);
- rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;
- sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp;
+ switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
+ case 1:
+ sys_info->freq_sdhc = freq_c_pll[1];
+ break;
+ case 2:
+ sys_info->freq_sdhc = freq_c_pll[1] / 2;
+ break;
+ case 3:
+ sys_info->freq_sdhc = freq_c_pll[1] / 3;
+ break;
+ case 6:
+ sys_info->freq_sdhc = freq_c_pll[0] / 2;
+ break;
+ default:
+ printf("Error: Unknown ESDHC clock select!\n");
+ break;
+ }
#else
sys_info->freq_sdhc = sys_info->freq_systembus;
#endif