armv8: fsl-layerscape: Add NXP LS2088A SoC support

[u-boot] / arch / arm / cpu / armv8 / fsl-layerscape / fsl_lsch2_speed.c

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index ea3723fe2e595e11944a56a47aac1b5912236e7d..55005f042049b56c8b9c044717d56bb019d77bff 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -11,6 +11,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/soc.h>
 #include <fsl_ifc.h>
+#include "cpu.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -24,6 +25,12 @@ void get_sys_info(struct sys_info *sys_info)
 #ifdef CONFIG_FSL_IFC
        struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
        u32 ccr;
+#endif
+#if (defined(CONFIG_FSL_ESDHC) &&\
+       defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\
+       defined(CONFIG_SYS_DPAA_FMAN)
+
+       u32 rcw_tmp;
 #endif
        struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
        unsigned int cpu;
@@ -41,7 +48,7 @@ void get_sys_info(struct sys_info *sys_info)
                [5] = 2,        /* CC2 PPL / 2 */
        };
 
-       uint i;
+       uint i, cluster;
        uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
        uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
        unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
@@ -53,12 +60,18 @@ void get_sys_info(struct sys_info *sys_info)
        sys_info->freq_ddrbus = sysclk;
 #endif
 
+#ifdef CONFIG_ARCH_LS1012A
+       sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
+                       FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
+                       FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
+#else
        sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
                        FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
                        FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
        sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
                        FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
                        FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
+#endif
 
        for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
                ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
@@ -68,8 +81,9 @@ void get_sys_info(struct sys_info *sys_info)
                        freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
        }
 
-       for (cpu = 0; cpu < CONFIG_MAX_CPUS; cpu++) {
-               u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
+       for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
+               cluster = fsl_qoriq_core_to_cluster(cpu);
+               u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
                                & 0xf;
                u32 cplx_pll = core_cplx_pll[c_pll_sel];
 
@@ -77,11 +91,66 @@ void get_sys_info(struct sys_info *sys_info)
                        freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
        }
 
+#ifdef CONFIG_ARCH_LS1012A
+       sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
+       sys_info->freq_ddrbus *= 2;
+#endif
+
 #define HWA_CGA_M1_CLK_SEL     0xe0000000
 #define HWA_CGA_M1_CLK_SHIFT   29
+#ifdef CONFIG_SYS_DPAA_FMAN
+       rcw_tmp = in_be32(&gur->rcwsr[7]);
+       switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
+       case 2:
+               sys_info->freq_fman[0] = freq_c_pll[0] / 2;
+               break;
+       case 3:
+               sys_info->freq_fman[0] = freq_c_pll[0] / 3;
+               break;
+       case 4:
+               sys_info->freq_fman[0] = freq_c_pll[0] / 4;
+               break;
+       case 5:
+               sys_info->freq_fman[0] = sys_info->freq_systembus;
+               break;
+       case 6:
+               sys_info->freq_fman[0] = freq_c_pll[1] / 2;
+               break;
+       case 7:
+               sys_info->freq_fman[0] = freq_c_pll[1] / 3;
+               break;
+       default:
+               printf("Error: Unknown FMan1 clock select!\n");
+               break;
+       }
+#endif
 
 #define HWA_CGA_M2_CLK_SEL     0x00000007
 #define HWA_CGA_M2_CLK_SHIFT   0
+#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+       rcw_tmp = in_be32(&gur->rcwsr[15]);
+       switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
+       case 1:
+               sys_info->freq_sdhc = freq_c_pll[1];
+               break;
+       case 2:
+               sys_info->freq_sdhc = freq_c_pll[1] / 2;
+               break;
+       case 3:
+               sys_info->freq_sdhc = freq_c_pll[1] / 3;
+               break;
+       case 6:
+               sys_info->freq_sdhc = freq_c_pll[0] / 2;
+               break;
+       default:
+               printf("Error: Unknown ESDHC clock select!\n");
+               break;
+       }
+#else
+       sys_info->freq_sdhc = sys_info->freq_systembus;
+#endif
+#endif
 
 #if defined(CONFIG_FSL_IFC)
        ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
@@ -100,6 +169,10 @@ int get_clocks(void)
        gd->bus_clk = sys_info.freq_systembus;
        gd->mem_clk = sys_info.freq_ddrbus;
 
+#ifdef CONFIG_FSL_ESDHC
+       gd->arch.sdhc_clk = sys_info.freq_sdhc;
+#endif
+
        if (gd->cpu_clk != 0)
                return 0;
        else
@@ -116,6 +189,13 @@ ulong get_ddr_freq(ulong dummy)
        return gd->mem_clk;
 }
 
+#ifdef CONFIG_FSL_ESDHC
+int get_sdhc_freq(ulong dummy)
+{
+       return gd->arch.sdhc_clk;
+}
+#endif
+
 int get_serial_clock(void)
 {
        return gd->bus_clk;
@@ -126,6 +206,10 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
        switch (clk) {
        case MXC_I2C_CLK:
                return get_bus_freq(0);
+#if defined(CONFIG_FSL_ESDHC)
+       case MXC_ESDHC_CLK:
+               return get_sdhc_freq(0);
+#endif
        case MXC_DSPI_CLK:
                return get_bus_freq(0);
        case MXC_UART_CLK: