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[u-boot] / arch / arm / cpu / armv8 / fsl-layerscape / lowlevel.S

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index a2185f2def23dce8fa508baf33c010aefdc85549..e9d373e4641fa4863cd33cd5f5225a8521956c61 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -1,8 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2014-2015 Freescale Semiconductor
  *
- * SPDX-License-Identifier:    GPL-2.0+
- *
  * Extracted from armv8/start.S
  */
 
@@ -37,9 +36,8 @@ ENTRY(get_gic_offset)
        ldr     x2, =DCFG_CCSR_SVR
        ldr     w2, [x2]
        rev     w2, w2
-       mov     w3, w2
-       ands    w3, w3, #SVR_WO_E << 8
-       mov     w4, #SVR_LS1043A << 8
+       lsr     w3, w2, #16
+       ldr     w4, =SVR_DEV(SVR_LS1043A)
        cmp     w3, w4
        b.ne    1f
        ands    w2, w2, #0xff
@@ -73,10 +71,13 @@ ENDPROC(smp_kick_all_cpus)
 ENTRY(lowlevel_init)
        mov     x29, lr                 /* Save LR */
 
-#ifdef CONFIG_FSL_LSCH3
+       switch_el x1, 1f, 100f, 100f    /* skip if not in EL3 */
+1:
+
+#if defined (CONFIG_SYS_FSL_HAS_CCN504)
 
        /* Set Wuo bit for RN-I 20 */
-#ifdef CONFIG_LS2080A
+#ifdef CONFIG_ARCH_LS2080A
        ldr     x0, =CCI_AUX_CONTROL_BASE(20)
        ldr     x1, =0x00000010
        bl      ccn504_set_aux
@@ -89,7 +90,7 @@ ENTRY(lowlevel_init)
         */
        bl      get_svr
        lsr     w0, w0, #16
-       ldr     w1, =SVR_DEV_LS2080A
+       ldr     w1, =SVR_DEV(SVR_LS2080A)
        cmp     w0, w1
        b.eq    1f
 
@@ -168,7 +169,7 @@ ENTRY(lowlevel_init)
        ldr     x0, =CCI_S2_QOS_CONTROL_BASE(20)
        ldr     x1, =0x00FF000C
        bl      ccn504_set_qos
-#endif
+#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
 
 #ifdef SMMU_BASE
        /* Set the SMMU page size in the sACR register */
@@ -193,6 +194,7 @@ ENTRY(lowlevel_init)
 #endif
 #endif
 
+100:
        branch_if_master x0, x1, 2f
 
 #if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
@@ -201,6 +203,8 @@ ENTRY(lowlevel_init)
 #endif
 
 2:
+       switch_el x1, 1f, 100f, 100f    /* skip if not in EL3 */
+1:
 #ifdef CONFIG_FSL_TZPC_BP147
        /* Set Non Secure access for all devices protected via TZPC */
        ldr     x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
@@ -218,7 +222,7 @@ ENTRY(lowlevel_init)
         */
        bl      get_svr
        lsr     w0, w0, #16
-       ldr     w1, =SVR_DEV_LS2080A
+       ldr     w1, =SVR_DEV(SVR_LS2080A)
        cmp     w0, w1
        b.eq    1f
 
@@ -229,43 +233,48 @@ ENTRY(lowlevel_init)
         * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
         *       placeholders.
         */
+#ifdef CONFIG_FSL_TZASC_1
        ldr     x1, =TZASC_GATE_KEEPER(0)
        ldr     w0, [x1]                /* Filter 0 Gate Keeper Register */
        orr     w0, w0, #1 << 0         /* Set open_request for Filter 0 */
        str     w0, [x1]
 
-       ldr     x1, =TZASC_GATE_KEEPER(1)
-       ldr     w0, [x1]                /* Filter 0 Gate Keeper Register */
-       orr     w0, w0, #1 << 0         /* Set open_request for Filter 0 */
-       str     w0, [x1]
-
        ldr     x1, =TZASC_REGION_ATTRIBUTES_0(0)
        ldr     w0, [x1]                /* Region-0 Attributes Register */
        orr     w0, w0, #1 << 31        /* Set Sec global write en, Bit[31] */
        orr     w0, w0, #1 << 30        /* Set Sec global read en, Bit[30] */
        str     w0, [x1]
 
+       ldr     x1, =TZASC_REGION_ID_ACCESS_0(0)
+       ldr     w0, [x1]                /* Region-0 Access Register */
+       mov     w0, #0xFFFFFFFF         /* Set nsaid_wr_en and nsaid_rd_en */
+       str     w0, [x1]
+#endif
+#ifdef CONFIG_FSL_TZASC_2
+       ldr     x1, =TZASC_GATE_KEEPER(1)
+       ldr     w0, [x1]                /* Filter 0 Gate Keeper Register */
+       orr     w0, w0, #1 << 0         /* Set open_request for Filter 0 */
+       str     w0, [x1]
+
        ldr     x1, =TZASC_REGION_ATTRIBUTES_0(1)
        ldr     w0, [x1]                /* Region-1 Attributes Register */
        orr     w0, w0, #1 << 31        /* Set Sec global write en, Bit[31] */
        orr     w0, w0, #1 << 30        /* Set Sec global read en, Bit[30] */
        str     w0, [x1]
 
-       ldr     x1, =TZASC_REGION_ID_ACCESS_0(0)
-       ldr     w0, [x1]                /* Region-0 Access Register */
-       mov     w0, #0xFFFFFFFF         /* Set nsaid_wr_en and nsaid_rd_en */
-       str     w0, [x1]
-
        ldr     x1, =TZASC_REGION_ID_ACCESS_0(1)
        ldr     w0, [x1]                /* Region-1 Attributes Register */
        mov     w0, #0xFFFFFFFF         /* Set nsaid_wr_en and nsaid_rd_en */
        str     w0, [x1]
-
+#endif
        isb
        dsb     sy
 #endif
+100:
 1:
 #ifdef CONFIG_ARCH_LS1046A
+       switch_el x1, 1f, 100f, 100f    /* skip if not in EL3 */
+1:
        /* Initialize the L2 RAM latency */
        mrs   x1, S3_1_c11_c0_2
        mov   x0, #0x1C7
@@ -277,6 +286,7 @@ ENTRY(lowlevel_init)
        orr   x1,  x1, #0x80
        msr   S3_1_c11_c0_2, x1
        isb
+100:
 #endif
 
 #if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
@@ -326,7 +336,9 @@ get_svr:
        ldr     x1, =FSL_LSCH3_SVR
        ldr     w0, [x1]
        ret
+#endif
 
+#ifdef CONFIG_SYS_FSL_HAS_CCN504
 hnf_pstate_poll:
        /* x0 has the desired status, return 0 for success, 1 for timeout
         * clobber x1, x2, x3, x4, x6, x7
@@ -377,7 +389,7 @@ ENTRY(__asm_flush_l3_dcache)
        /*
         * Return status in x0
         *    success 0
-        *    tmeout 1 for setting SFONLY, 2 for FAM, 3 for both
+        *    timeout 1 for setting SFONLY, 2 for FAM, 3 for both
         */
        mov     x29, lr
        mov     x8, #0
@@ -404,7 +416,7 @@ ENTRY(__asm_flush_l3_dcache)
        mov     lr, x29
        ret
 ENDPROC(__asm_flush_l3_dcache)
-#endif
+#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
 
 #ifdef CONFIG_MP
        /* Keep literals not used by the secondary boot code outside it */
@@ -481,9 +493,7 @@ slave_cpu:
        rev     x0, x0                  /* BE to LE conversion */
 cpu_is_le:
        ldr     x5, [x11, #24]
-       ldr     x6, =IH_ARCH_DEFAULT
-       cmp     x6, x5
-       b.eq    1f
+       cbz     x5, 1f
 
 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
        adr     x4, secondary_switch_to_el1
@@ -525,9 +535,7 @@ ENTRY(secondary_switch_to_el1)
        ldr     x4, [x11]
 
        ldr     x5, [x11, #24]
-       ldr     x6, =IH_ARCH_DEFAULT
-       cmp     x6, x5
-       b.eq    2f
+       cbz     x5, 2f
 
        ldr     x5, =ES_TO_AARCH32
        bl      switch_to_el1