armv8: fsl-layerscape: Add NXP LS2088A SoC support

[u-boot] / arch / arm / cpu / armv8 / fsl-layerscape / lowlevel.S

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 6ff47b0e0600ad8b5681c689e290921d68f2cec8..f7b49cb9fe6fbca308396ed1a338590eee8e3983 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -15,6 +15,7 @@
 #endif
 #ifdef CONFIG_FSL_LSCH3
 #include <asm/arch-fsl-layerscape/immap_lsch3.h>
+#include <asm/arch-fsl-layerscape/soc.h>
 #endif
 
 ENTRY(lowlevel_init)
@@ -140,6 +141,16 @@ ENTRY(lowlevel_init)
 #endif
 
 #ifdef CONFIG_FSL_TZASC_400
+       /*
+        * LS2080 and its personalities does not support TZASC
+        * So skip TZASC related operations
+        */
+       bl      get_svr
+       lsr     w0, w0, #16
+       ldr     w1, =SVR_DEV_LS2080A
+       cmp     w0, w1
+       b.eq    1f
+
        /* Set TZASC so that:
         * a. We use only Region0 whose global secure write/read is EN
         * b. We use only Region0 whose NSAID write/read is EN
@@ -148,26 +159,26 @@ ENTRY(lowlevel_init)
         *       placeholders.
         */
        ldr     x1, =TZASC_GATE_KEEPER(0)
-       ldr     x0, [x1]                /* Filter 0 Gate Keeper Register */
-       orr     x0, x0, #1 << 0         /* Set open_request for Filter 0 */
-       str     x0, [x1]
+       ldr     w0, [x1]                /* Filter 0 Gate Keeper Register */
+       orr     w0, w0, #1 << 0         /* Set open_request for Filter 0 */
+       str     w0, [x1]
 
        ldr     x1, =TZASC_GATE_KEEPER(1)
-       ldr     x0, [x1]                /* Filter 0 Gate Keeper Register */
-       orr     x0, x0, #1 << 0         /* Set open_request for Filter 0 */
-       str     x0, [x1]
+       ldr     w0, [x1]                /* Filter 0 Gate Keeper Register */
+       orr     w0, w0, #1 << 0         /* Set open_request for Filter 0 */
+       str     w0, [x1]
 
        ldr     x1, =TZASC_REGION_ATTRIBUTES_0(0)
-       ldr     x0, [x1]                /* Region-0 Attributes Register */
-       orr     x0, x0, #1 << 31        /* Set Sec global write en, Bit[31] */
-       orr     x0, x0, #1 << 30        /* Set Sec global read en, Bit[30] */
-       str     x0, [x1]
+       ldr     w0, [x1]                /* Region-0 Attributes Register */
+       orr     w0, w0, #1 << 31        /* Set Sec global write en, Bit[31] */
+       orr     w0, w0, #1 << 30        /* Set Sec global read en, Bit[30] */
+       str     w0, [x1]
 
        ldr     x1, =TZASC_REGION_ATTRIBUTES_0(1)
-       ldr     x0, [x1]                /* Region-1 Attributes Register */
-       orr     x0, x0, #1 << 31        /* Set Sec global write en, Bit[31] */
-       orr     x0, x0, #1 << 30        /* Set Sec global read en, Bit[30] */
-       str     x0, [x1]
+       ldr     w0, [x1]                /* Region-1 Attributes Register */
+       orr     w0, w0, #1 << 31        /* Set Sec global write en, Bit[31] */
+       orr     w0, w0, #1 << 30        /* Set Sec global read en, Bit[30] */
+       str     w0, [x1]
 
        ldr     x1, =TZASC_REGION_ID_ACCESS_0(0)
        ldr     w0, [x1]                /* Region-0 Access Register */
@@ -182,7 +193,7 @@ ENTRY(lowlevel_init)
        isb
        dsb     sy
 #endif
-
+1:
 #ifdef CONFIG_ARCH_LS1046A
        /* Initialize the L2 RAM latency */
        mrs   x1, S3_1_c11_c0_2