common: Fix cpu nr type which is always unsigned type

[u-boot] / arch / arm / cpu / armv8 / fsl-layerscape / mp.c

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
index 0d600db09054570213623c1692248aa4d6df448b..7627fd13e7d87995c2d19ae2ed4a6c38a279b439 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -9,6 +8,8 @@
 #include <asm/system.h>
 #include <asm/arch/mp.h>
 #include <asm/arch/soc.h>
+#include "cpu.h"
+#include <asm/arch-fsl-layerscape/soc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -22,11 +23,54 @@ phys_addr_t determine_mp_bootpg(void)
        return (phys_addr_t)&secondary_boot_code;
 }
 
+void update_os_arch_secondary_cores(uint8_t os_arch)
+{
+       u64 *table = get_spin_tbl_addr();
+       int i;
+
+       for (i = 1; i < CONFIG_MAX_CPUS; i++) {
+               if (os_arch == IH_ARCH_DEFAULT)
+                       table[i * WORDS_PER_SPIN_TABLE_ENTRY +
+                               SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_SAME;
+               else
+                       table[i * WORDS_PER_SPIN_TABLE_ENTRY +
+                               SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_DIFF;
+       }
+}
+
+#ifdef CONFIG_FSL_LSCH3
+void wake_secondary_core_n(int cluster, int core, int cluster_cores)
+{
+       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+       struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
+       u32 mpidr = 0;
+
+       mpidr = ((cluster << 8) | core);
+       /*
+        * mpidr_el1 register value of core which needs to be released
+        * is written to scratchrw[6] register
+        */
+       gur_out32(&gur->scratchrw[6], mpidr);
+       asm volatile("dsb st" : : : "memory");
+       rst->brrl |= 1 << ((cluster * cluster_cores) + core);
+       asm volatile("dsb st" : : : "memory");
+       /*
+        * scratchrw[6] register value is polled
+        * when the value becomes zero, this means that this core is up
+        * and running, next core can be released now
+        */
+       while (gur_in32(&gur->scratchrw[6]) != 0)
+               ;
+}
+#endif
+
 int fsl_layerscape_wake_seconday_cores(void)
 {
        struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 #ifdef CONFIG_FSL_LSCH3
        struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
+       u32 svr, ver, cluster, type;
+       int j = 0, cluster_cores = 0;
 #elif defined(CONFIG_FSL_LSCH2)
        struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
 #endif
@@ -55,10 +99,40 @@ int fsl_layerscape_wake_seconday_cores(void)
 #ifdef CONFIG_FSL_LSCH3
        gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
        gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr);
-       gur_out32(&gur->scratchrw[6], 1);
-       asm volatile("dsb st" : : : "memory");
-       rst->brrl = cores;
-       asm volatile("dsb st" : : : "memory");
+
+       svr = gur_in32(&gur->svr);
+       ver = SVR_SOC_VER(svr);
+       if (ver == SVR_LS2080A || ver == SVR_LS2085A) {
+               gur_out32(&gur->scratchrw[6], 1);
+               asm volatile("dsb st" : : : "memory");
+               rst->brrl = cores;
+               asm volatile("dsb st" : : : "memory");
+       } else {
+               /*
+                * Release the cores out of reset one-at-a-time to avoid
+                * power spikes
+                */
+               i = 0;
+               cluster = in_le32(&gur->tp_cluster[i].lower);
+               for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+                       type = initiator_type(cluster, j);
+                       if (type &&
+                           TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
+                               cluster_cores++;
+               }
+
+               do {
+                       cluster = in_le32(&gur->tp_cluster[i].lower);
+                       for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+                               type = initiator_type(cluster, j);
+                               if (type &&
+                                   TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
+                                       wake_secondary_core_n(i, j,
+                                                             cluster_cores);
+                       }
+               i++;
+               } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
+       }
 #elif defined(CONFIG_FSL_LSCH2)
        scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32));
        scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr);
@@ -104,6 +178,11 @@ int is_core_valid(unsigned int core)
        return !!((1 << core) & cpu_mask());
 }
 
+static int is_pos_valid(unsigned int pos)
+{
+       return !!((1 << pos) & cpu_pos_mask());
+}
+
 int is_core_online(u64 cpu_id)
 {
        u64 *table;
@@ -112,23 +191,23 @@ int is_core_online(u64 cpu_id)
        return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1;
 }
 
-int cpu_reset(int nr)
+int cpu_reset(u32 nr)
 {
        puts("Feature is not implemented.\n");
 
        return 0;
 }
 
-int cpu_disable(int nr)
+int cpu_disable(u32 nr)
 {
        puts("Feature is not implemented.\n");
 
        return 0;
 }
 
-int core_to_pos(int nr)
+static int core_to_pos(int nr)
 {
-       u32 cores = cpu_mask();
+       u32 cores = cpu_pos_mask();
        int i, count = 0;
 
        if (nr == 0) {
@@ -139,17 +218,20 @@ int core_to_pos(int nr)
        }
 
        for (i = 1; i < 32; i++) {
-               if (is_core_valid(i)) {
+               if (is_pos_valid(i)) {
                        count++;
                        if (count == nr)
                                break;
                }
        }
 
-       return count;
+       if (count != nr)
+               return -1;
+
+       return i;
 }
 
-int cpu_status(int nr)
+int cpu_status(u32 nr)
 {
        u64 *table;
        int pos;
@@ -175,7 +257,7 @@ int cpu_status(int nr)
        return 0;
 }
 
-int cpu_release(int nr, int argc, char * const argv[])
+int cpu_release(u32 nr, int argc, char * const argv[])
 {
        u64 boot_addr;
        u64 *table = (u64 *)get_spin_tbl_addr();
@@ -192,6 +274,12 @@ int cpu_release(int nr, int argc, char * const argv[])
                           (unsigned long)table + SPIN_TABLE_ELEM_SIZE);
        asm volatile("dsb st");
        smp_kick_all_cpus();    /* only those with entry addr set will run */
+       /*
+        * When the first release command runs, all cores are set to go. Those
+        * without a valid entry address will be trapped by "wfe". "sev" kicks
+        * them off to check the address again. When set, they continue to run.
+        */
+       asm volatile("sev");
 
        return 0;
 }