Merge branch 'master' of git://git.denx.de/u-boot-net

[u-boot] / arch / arm / cpu / armv8 / fsl-layerscape / soc.c

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 7ff01481bef68b2ebbf0b3fbd0ba960288e7bd37..0cb010012e7add46e725741cbcb535e2bb9047f4 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -18,7 +18,31 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+bool soc_has_dp_ddr(void)
+{
+       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+       u32 svr = gur_in32(&gur->svr);
+
+       /* LS2085A has DP_DDR */
+       if (SVR_SOC_VER(svr) == SVR_LS2085)
+               return true;
+
+       return false;
+}
+
+bool soc_has_aiop(void)
+{
+       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+       u32 svr = gur_in32(&gur->svr);
+
+       /* LS2085A has AIOP */
+       if (SVR_SOC_VER(svr) == SVR_LS2085)
+               return true;
+
+       return false;
+}
+
+#ifdef CONFIG_LS2080A
 /*
  * This erratum requires setting a value to eddrtqcr1 to
  * optimal the DDR performance.
@@ -151,7 +175,14 @@ static void erratum_a009203(void)
 #endif
 #endif
 }
-
+void bypass_smmu(void)
+{
+       u32 val;
+       val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+       out_le32(SMMU_SCR0, val);
+       val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+       out_le32(SMMU_NSCR0, val);
+}
 void fsl_lsch3_early_init_f(void)
 {
        erratum_a008751();
@@ -160,6 +191,15 @@ void fsl_lsch3_early_init_f(void)
        erratum_a009203();
        erratum_a008514();
        erratum_a008336();
+#ifdef CONFIG_CHAIN_OF_TRUST
+       /* In case of Secure Boot, the IBR configures the SMMU
+       * to allow only Secure transactions.
+       * SMMU must be reset in bypass mode.
+       * Set the ClientPD bit and Clear the USFCFG Bit
+       */
+       if (fsl_check_boot_mode_secure() == 1)
+               bypass_smmu();
+#endif
 }
 
 #ifdef CONFIG_SCSI_AHCI_PLAT
@@ -213,6 +253,24 @@ static void erratum_a009929(void)
 #endif
 }
 
+/*
+ * This erratum requires setting a value to eddrtqcr1 to optimal
+ * the DDR performance. The eddrtqcr1 register is in SCFG space
+ * of LS1043A and the offset is 0x157_020c.
+ */
+#if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
+       && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
+#error A009660 and A008514 can not be both enabled.
+#endif
+
+static void erratum_a009660(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009660
+       u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
+       out_be32(eddrtqcr1, 0x63b20042);
+#endif
+}
+
 void fsl_lsch2_early_init_f(void)
 {
        struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -222,7 +280,7 @@ void fsl_lsch2_early_init_f(void)
        init_early_memctl_regs();       /* tighten IFC timing */
 #endif
 
-#ifdef CONFIG_FSL_QSPI
+#if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
        out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 #endif
        /* Make SEC reads and writes snoopable */
@@ -238,6 +296,7 @@ void fsl_lsch2_early_init_f(void)
 
        /* Erratum */
        erratum_a009929();
+       erratum_a009660();
 }
 #endif