armv8: lsch3: Use SVR based timer base address detection

[u-boot] / arch / arm / cpu / armv8 / fsl-layerscape / soc.c

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 463d1e30d2c3966b1b858c28af43f7d9535a25d3..5a4dd39a6173e785348bb65c7ddd30f303dcaab6 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -50,16 +50,16 @@ bool soc_has_aiop(void)
        return false;
 }
 
-#ifdef CONFIG_LS2080A
+#if defined(CONFIG_FSL_LSCH3)
 /*
  * This erratum requires setting a value to eddrtqcr1 to
  * optimal the DDR performance.
  */
 static void erratum_a008336(void)
 {
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
        u32 *eddrtqcr1;
 
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
        eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
        if (fsl_ddr_get_version(0) == 0x50200)
@@ -79,9 +79,9 @@ static void erratum_a008336(void)
  */
 static void erratum_a008514(void)
 {
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
        u32 *eddrtqcr1;
 
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
        eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
        out_le32(eddrtqcr1, 0x63b20002);
@@ -176,6 +176,7 @@ static void erratum_a009203(void)
 #endif
 #endif
 }
+
 void bypass_smmu(void)
 {
        u32 val;
@@ -233,9 +234,8 @@ int sata_init(void)
        out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
 #endif
        out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
-       out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
-       out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
        out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
+       out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
        ahci_init((void __iomem *)CONFIG_SYS_SATA);
        scsi_scan(0);
@@ -321,6 +321,19 @@ void erratum_a010315(void)
 }
 #endif
 
+static void erratum_a010539(void)
+{
+#if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
+       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+       u32 porsr1;
+
+       porsr1 = in_be32(&gur->porsr1);
+       porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
+       out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
+                porsr1);
+#endif
+}
+
 void fsl_lsch2_early_init_f(void)
 {
        struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -339,7 +352,9 @@ void fsl_lsch2_early_init_f(void)
 #endif
        /* Make SEC reads and writes snoopable */
        setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
-                    SCFG_SNPCNFGCR_SECWRSNP);
+                    SCFG_SNPCNFGCR_SECWRSNP |
+                    SCFG_SNPCNFGCR_SATARDSNP |
+                    SCFG_SNPCNFGCR_SATAWRSNP);
 
        /*
         * Enable snoop requests and DVM message requests for
@@ -352,6 +367,7 @@ void fsl_lsch2_early_init_f(void)
        erratum_a008850_early(); /* part 1 of 2 */
        erratum_a009929();
        erratum_a009660();
+       erratum_a010539();
 }
 #endif