Merge git://www.denx.de/git/u-boot-imx

[u-boot] / arch / arm / cpu / armv8 / fsl-layerscape / soc.c

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index b54a9379711752e1dd78184121884954b08d4ff5..639e9d2ddc8d643904f22872b42fbd21a66d29ff 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -95,7 +95,7 @@ static void erratum_a008514(void)
 
 static unsigned long get_internval_val_mhz(void)
 {
-       char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);
+       char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
        /*
         *  interval is the number of platform cycles(MHz) between
         *  wake up events generated by EPU.
@@ -134,7 +134,7 @@ void erratum_a009635(void)
 
 static void erratum_rcw_src(void)
 {
-#if defined(CONFIG_SPL)
+#if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
        u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
        u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
        u32 val;
@@ -152,6 +152,7 @@ static void erratum_rcw_src(void)
  * This erratum requires setting glitch_en bit to enable
  * digital glitch filter to improve clock stability.
  */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
 static void erratum_a009203(void)
 {
        u8 __iomem *ptr;
@@ -178,6 +179,7 @@ static void erratum_a009203(void)
 #endif
 #endif
 }
+#endif
 
 void bypass_smmu(void)
 {
@@ -191,7 +193,9 @@ void fsl_lsch3_early_init_f(void)
 {
        erratum_rcw_src();
        init_early_memctl_regs();       /* tighten IFC timing */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
        erratum_a009203();
+#endif
        erratum_a008514();
        erratum_a008336();
 #ifdef CONFIG_CHAIN_OF_TRUST
@@ -221,7 +225,7 @@ int sata_init(void)
        out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
        ahci_init((void __iomem *)CONFIG_SYS_SATA1);
-       scsi_scan(0);
+       scsi_scan(false);
 
        return 0;
 }
@@ -240,7 +244,7 @@ int sata_init(void)
        out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
        ahci_init((void __iomem *)CONFIG_SYS_SATA);
-       scsi_scan(0);
+       scsi_scan(false);
 
        return 0;
 }
@@ -284,6 +288,10 @@ static void erratum_a008850_early(void)
        struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
        struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
 
+       /* Skip if running at lower exception level */
+       if (current_el() < 3)
+               return;
+
        /* disables propagation of barrier transactions to DDRC from CCI400 */
        out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 
@@ -300,6 +308,10 @@ void erratum_a008850_post(void)
        struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
        u32 tmp;
 
+       /* Skip if running at lower exception level */
+       if (current_el() < 3)
+               return;
+
        /* enable propagation of barrier transactions to DDRC from CCI400 */
        out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 
@@ -451,8 +463,10 @@ void fsl_lsch2_early_init_f(void)
         * Enable snoop requests and DVM message requests for
         * Slave insterface S4 (A53 core cluster)
         */
-       out_le32(&cci->slave[4].snoop_ctrl,
-                CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+       if (current_el() == 3) {
+               out_le32(&cci->slave[4].snoop_ctrl,
+                        CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+       }
 
        /* Erratum */
        erratum_a008850_early(); /* part 1 of 2 */