arm64/ls1046a: Enable ERRATUM_A008850 for ls1046a SoC

[u-boot] / arch / arm / cpu / armv8 / fsl-layerscape / soc.c

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 6c4238707d1c32a44a16c3da479bd495b4386478..9e3cdd78af5b6f70fffc9298801c69331f599462 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -152,6 +152,7 @@ static void erratum_rcw_src(void)
  * This erratum requires setting glitch_en bit to enable
  * digital glitch filter to improve clock stability.
  */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
 static void erratum_a009203(void)
 {
        u8 __iomem *ptr;
@@ -178,6 +179,7 @@ static void erratum_a009203(void)
 #endif
 #endif
 }
+#endif
 
 void bypass_smmu(void)
 {
@@ -191,7 +193,9 @@ void fsl_lsch3_early_init_f(void)
 {
        erratum_rcw_src();
        init_early_memctl_regs();       /* tighten IFC timing */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
        erratum_a009203();
+#endif
        erratum_a008514();
        erratum_a008336();
 #ifdef CONFIG_CHAIN_OF_TRUST
@@ -213,10 +217,12 @@ int sata_init(void)
        ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
        out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
        out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
+       out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
        ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
        out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
        out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
+       out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
        ahci_init((void __iomem *)CONFIG_SYS_SATA1);
        scsi_scan(0);
@@ -231,10 +237,8 @@ int sata_init(void)
 {
        struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
 
-#ifdef CONFIG_ARCH_LS1046A
        /* Disable SATA ECC */
        out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
-#endif
        out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
        out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
        out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
@@ -336,6 +340,95 @@ static void erratum_a010539(void)
 #endif
 }
 
+/* Get VDD in the unit mV from voltage ID */
+int get_core_volt_from_fuse(void)
+{
+       struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+       int vdd;
+       u32 fusesr;
+       u8 vid;
+
+       fusesr = in_be32(&gur->dcfg_fusesr);
+       debug("%s: fusesr = 0x%x\n", __func__, fusesr);
+       vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
+               FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
+       if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
+               vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
+                       FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
+       }
+       debug("%s: VID = 0x%x\n", __func__, vid);
+       switch (vid) {
+       case 0x00: /* VID isn't supported */
+               vdd = -EINVAL;
+               debug("%s: The VID feature is not supported\n", __func__);
+               break;
+       case 0x08: /* 0.9V silicon */
+               vdd = 900;
+               break;
+       case 0x10: /* 1.0V silicon */
+               vdd = 1000;
+               break;
+       default:  /* Other core voltage */
+               vdd = -EINVAL;
+               printf("%s: The VID(%x) isn't supported\n", __func__, vid);
+               break;
+       }
+       debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
+
+       return vdd;
+}
+
+__weak int board_switch_core_volt(u32 vdd)
+{
+       return 0;
+}
+
+static int setup_core_volt(u32 vdd)
+{
+       return board_setup_core_volt(vdd);
+}
+
+#ifdef CONFIG_SYS_FSL_DDR
+static void ddr_enable_0v9_volt(bool en)
+{
+       struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+       u32 tmp;
+
+       tmp = ddr_in32(&ddr->ddr_cdr1);
+
+       if (en)
+               tmp |= DDR_CDR1_V0PT9_EN;
+       else
+               tmp &= ~DDR_CDR1_V0PT9_EN;
+
+       ddr_out32(&ddr->ddr_cdr1, tmp);
+}
+#endif
+
+int setup_chip_volt(void)
+{
+       int vdd;
+
+       vdd = get_core_volt_from_fuse();
+       /* Nothing to do for silicons doesn't support VID */
+       if (vdd < 0)
+               return vdd;
+
+       if (setup_core_volt(vdd))
+               printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
+#ifdef CONFIG_SYS_HAS_SERDES
+       if (setup_serdes_volt(vdd))
+               printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
+#endif
+
+#ifdef CONFIG_SYS_FSL_DDR
+       if (vdd == 900)
+               ddr_enable_0v9_volt(true);
+#endif
+
+       return 0;
+}
+
 void fsl_lsch2_early_init_f(void)
 {
        struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -373,6 +466,45 @@ void fsl_lsch2_early_init_f(void)
 }
 #endif
 
+#ifdef CONFIG_QSPI_AHB_INIT
+/* Enable 4bytes address support and fast read */
+int qspi_ahb_init(void)
+{
+       u32 *qspi_lut, lut_key, *qspi_key;
+
+       qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
+       qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
+
+       lut_key = in_be32(qspi_key);
+
+       if (lut_key == 0x5af05af0) {
+               /* That means the register is BE */
+               out_be32(qspi_key, 0x5af05af0);
+               /* Unlock the lut table */
+               out_be32(qspi_key + 1, 0x00000002);
+               out_be32(qspi_lut, 0x0820040c);
+               out_be32(qspi_lut + 1, 0x1c080c08);
+               out_be32(qspi_lut + 2, 0x00002400);
+               /* Lock the lut table */
+               out_be32(qspi_key, 0x5af05af0);
+               out_be32(qspi_key + 1, 0x00000001);
+       } else {
+               /* That means the register is LE */
+               out_le32(qspi_key, 0x5af05af0);
+               /* Unlock the lut table */
+               out_le32(qspi_key + 1, 0x00000002);
+               out_le32(qspi_lut, 0x0820040c);
+               out_le32(qspi_lut + 1, 0x1c080c08);
+               out_le32(qspi_lut + 2, 0x00002400);
+               /* Lock the lut table */
+               out_le32(qspi_key, 0x5af05af0);
+               out_le32(qspi_key + 1, 0x00000001);
+       }
+
+       return 0;
+}
+#endif
+
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
@@ -382,6 +514,9 @@ int board_late_init(void)
 #ifdef CONFIG_CHAIN_OF_TRUST
        fsl_setenv_chain_of_trust();
 #endif
+#ifdef CONFIG_QSPI_AHB_INIT
+       qspi_ahb_init();
+#endif
 
        return 0;
 }