arm64: zynqmp: Wire SD1 level shifter mode to SPL

[u-boot] / arch / arm / cpu / armv8 / start.S

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 953505735523d07a9c251b0d269502056b881645..5c500be51d1f5fb616e04539e5fd2cb9e7287e3b 100644 (file)
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -85,6 +85,20 @@ save_boot_params_ret:
        msr     cpacr_el1, x0                   /* Enable FP/SIMD */
 0:
 
+       /*
+        * Enable SMPEN bit for coherency.
+        * This register is not architectural but at the moment
+        * this bit should be set for A53/A57/A72.
+        */
+#ifdef CONFIG_ARMV8_SET_SMPEN
+       switch_el x1, 3f, 1f, 1f
+3:
+       mrs     x0, S3_1_c15_c2_1               /* cpuectlr_el1 */
+       orr     x0, x0, #0x40
+       msr     S3_1_c15_c2_1, x0
+1:
+#endif
+
        /* Apply ARM core specific erratas */
        bl      apply_core_errata
 
@@ -250,14 +264,14 @@ WEAK(lowlevel_init)
        /*
         * All slaves will enter EL2 and optionally EL1.
         */
-       adr     x3, lowlevel_in_el2
-       ldr     x4, =ES_TO_AARCH64
+       adr     x4, lowlevel_in_el2
+       ldr     x5, =ES_TO_AARCH64
        bl      armv8_switch_to_el2
 
 lowlevel_in_el2:
 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
-       adr     x3, lowlevel_in_el1
-       ldr     x4, =ES_TO_AARCH64
+       adr     x4, lowlevel_in_el1
+       ldr     x5, =ES_TO_AARCH64
        bl      armv8_switch_to_el1
 
 lowlevel_in_el1: