arm64: zynqmp: Wire SD1 level shifter mode to SPL

[u-boot] / arch / arm / cpu / armv8 / start.S

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index dfce469206681acf558760c4faa9d6ef22c00010..5c500be51d1f5fb616e04539e5fd2cb9e7287e3b 100644 (file)
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -19,8 +19,6 @@
 
 .globl _start
 _start:
-       b       reset
-
 #ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK
 /*
  * Various SoCs need something special and SoC-specific up front in
@@ -28,7 +26,8 @@ _start:
  * use it here.
  */
 #include <asm/arch/boot0.h>
-ARM_SOC_BOOT0_HOOK
+#else
+       b       reset
 #endif
 
        .align 3
@@ -53,6 +52,11 @@ _bss_end_ofs:
        .quad   __bss_end - _start
 
 reset:
+       /* Allow the board to save important registers */
+       b       save_boot_params
+.globl save_boot_params_ret
+save_boot_params_ret:
+
 #ifdef CONFIG_SYS_RESET_SCTRL
        bl reset_sctrl
 #endif
@@ -81,13 +85,19 @@ reset:
        msr     cpacr_el1, x0                   /* Enable FP/SIMD */
 0:
 
-       /* Enalbe SMPEN bit for coherency.
+       /*
+        * Enable SMPEN bit for coherency.
         * This register is not architectural but at the moment
         * this bit should be set for A53/A57/A72.
         */
-       mrs     x0, S3_1_c15_c2_1               /* cpuactlr_el1 */
+#ifdef CONFIG_ARMV8_SET_SMPEN
+       switch_el x1, 3f, 1f, 1f
+3:
+       mrs     x0, S3_1_c15_c2_1               /* cpuectlr_el1 */
        orr     x0, x0, #0x40
        msr     S3_1_c15_c2_1, x0
+1:
+#endif
 
        /* Apply ARM core specific erratas */
        bl      apply_core_errata
@@ -102,7 +112,11 @@ reset:
        /* Processor specific initialization */
        bl      lowlevel_init
 
-#ifdef CONFIG_ARMV8_MULTIENTRY
+#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD)
+       branch_if_master x0, x1, master_cpu
+       b       spin_table_secondary_jump
+       /* never return */
+#elif defined(CONFIG_ARMV8_MULTIENTRY)
        branch_if_master x0, x1, master_cpu
 
        /*
@@ -114,10 +128,8 @@ slave_cpu:
        ldr     x0, [x1]
        cbz     x0, slave_cpu
        br      x0                      /* branch to the given address */
-master_cpu:
-       /* On the master CPU */
 #endif /* CONFIG_ARMV8_MULTIENTRY */
-
+master_cpu:
        bl      _main
 
 #ifdef CONFIG_SYS_RESET_SCTRL
@@ -252,9 +264,17 @@ WEAK(lowlevel_init)
        /*
         * All slaves will enter EL2 and optionally EL1.
         */
+       adr     x4, lowlevel_in_el2
+       ldr     x5, =ES_TO_AARCH64
        bl      armv8_switch_to_el2
+
+lowlevel_in_el2:
 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+       adr     x4, lowlevel_in_el1
+       ldr     x5, =ES_TO_AARCH64
        bl      armv8_switch_to_el1
+
+lowlevel_in_el1:
 #endif
 
 #endif /* CONFIG_ARMV8_MULTIENTRY */
@@ -288,3 +308,7 @@ ENTRY(c_runtime_cpu_setup)
 
        ret
 ENDPROC(c_runtime_cpu_setup)
+
+WEAK(save_boot_params)
+       b       save_boot_params_ret    /* back to my caller */
+ENDPROC(save_boot_params)