armv8: layerscape: Update early MMU for DDR after initialization

[u-boot] / arch / arm / cpu / armv8 / start.S

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 530870278c33c5eaac01dfb5332e527eb4736224..62d97f7e882225a027390e8d2b6f13c4a6a606de 100644 (file)
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -19,8 +19,6 @@
 
 .globl _start
 _start:
-       b       reset
-
 #ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK
 /*
  * Various SoCs need something special and SoC-specific up front in
@@ -28,7 +26,8 @@ _start:
  * use it here.
  */
 #include <asm/arch/boot0.h>
-ARM_SOC_BOOT0_HOOK
+#else
+       b       reset
 #endif
 
        .align 3
@@ -110,7 +109,7 @@ save_boot_params_ret:
        /* Processor specific initialization */
        bl      lowlevel_init
 
-#if CONFIG_IS_ENABLED(ARMV8_SPIN_TABLE)
+#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD)
        branch_if_master x0, x1, master_cpu
        b       spin_table_secondary_jump
        /* never return */
@@ -262,14 +261,14 @@ WEAK(lowlevel_init)
        /*
         * All slaves will enter EL2 and optionally EL1.
         */
-       adr     x3, lowlevel_in_el2
-       ldr     x4, =ES_TO_AARCH64
+       adr     x4, lowlevel_in_el2
+       ldr     x5, =ES_TO_AARCH64
        bl      armv8_switch_to_el2
 
 lowlevel_in_el2:
 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
-       adr     x3, lowlevel_in_el1
-       ldr     x4, =ES_TO_AARCH64
+       adr     x4, lowlevel_in_el1
+       ldr     x5, =ES_TO_AARCH64
        bl      armv8_switch_to_el1
 
 lowlevel_in_el1: