ARM: */start.S: code cleanup

[u-boot] / arch / arm / cpu / sa1100 / start.S

diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S
index 1246b7831ae376e29cef8fab9da50e4ccffabe9e..815d70488be5bf48cd1af7a6bc7f6e6cb0b69e38 100644 (file)
--- a/arch/arm/cpu/sa1100/start.S
+++ b/arch/arm/cpu/sa1100/start.S
@@ -158,7 +158,6 @@ stack_setup:
        cmp     r0, r6
        beq     clear_bss               /* skip relocation */
        mov     r1, r6                  /* r1 <- scratch for copy_loop */
-       ldr     r2, _TEXT_BASE
        ldr     r3, _bss_start_ofs
        add     r2, r0, r3              /* r2 <- source end address         */
 
@@ -184,10 +183,10 @@ fixloop:
        ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
        add     r0, r0, r9              /* r0 <- location to fix up in RAM */
        ldr     r1, [r2, #4]
-       and     r8, r1, #0xff
-       cmp     r8, #23                 /* relative fixup? */
+       and     r7, r1, #0xff
+       cmp     r7, #23                 /* relative fixup? */
        beq     fixrel
-       cmp     r8, #2                  /* absolute fixup? */
+       cmp     r7, #2                  /* absolute fixup? */
        beq     fixabs
        /* ignore unknown type of fixup */
        b       fixnext
@@ -196,7 +195,7 @@ fixabs:
        mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
        add     r1, r10, r1             /* r1 <- address of symbol in table */
        ldr     r1, [r1, #4]            /* r1 <- symbol value */
-       add     r1, r9                  /* r1 <- relocated sym addr */
+       add     r1, r1, r9              /* r1 <- relocated sym addr */
        b       fixnext
 fixrel:
        /* relative fix: increase location by offset */
@@ -213,7 +212,6 @@ clear_bss:
 #ifndef CONFIG_PRELOADER
        ldr     r0, _bss_start_ofs
        ldr     r1, _bss_end_ofs
-       ldr     r3, _TEXT_BASE          /* Text base */
        mov     r4, r6                  /* reloc addr */
        add     r0, r0, r4
        add     r1, r1, r4