* (C) Copyright 2010-2011
* NVIDIA Corporation <www.nvidia.com>
*
-* See file CREDITS for list of people who contributed to this
-* project.
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation; either version 2 of
-* the License, or (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-* MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
/* Tegra AP (Application Processor) code */
switch (chip_id) {
case CHIPID_TEGRA20:
switch (sku_id) {
+ case SKU_ID_T20_7:
case SKU_ID_T20:
return TEGRA_SOC_T20;
case SKU_ID_T25SE:
case CHIPID_TEGRA114:
switch (sku_id) {
case SKU_ID_T114_ENG:
+ case SKU_ID_T114_1:
return TEGRA_SOC_T114;
}
break;
struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
u32 reg;
+ /* Only enable the SCU on T20/T25 */
+ if (tegra_get_chip() != CHIPID_TEGRA20)
+ return;
+
/* If SCU already setup/enabled, return */
if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
return;