Merge branch 'master' of git://git.denx.de/u-boot-arm

[u-boot] / arch / arm / cpu / tegra114-common / clock.c

diff --git a/arch/arm/cpu/tegra114-common/clock.c b/arch/arm/cpu/tegra114-common/clock.c
index 47612e12d262a7686025bdddd5307f4fdb7c6803..d5194e11b5fd88e8269b64b6de704922cdddf2e1 100644 (file)
--- a/arch/arm/cpu/tegra114-common/clock.c
+++ b/arch/arm/cpu/tegra114-common/clock.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -103,7 +103,7 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
                MASK_BITS_31_29},
        { CLK(PERIPH),  CLK(CGENERAL),  CLK(SFROM32KHZ),        CLK(OSC),
                CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
-               MASK_BITS_29_28}
+               MASK_BITS_31_28}
 };
 
 /*
@@ -604,26 +604,24 @@ void clock_early_init(void)
        struct clk_rst_ctlr *clkrst =
                (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
 
+       tegra30_set_up_pllp();
+
        /*
-        * PLLP output frequency set to 408Mhz
         * PLLC output frequency set to 600Mhz
         * PLLD output frequency set to 925Mhz
         */
        switch (clock_get_osc_freq()) {
        case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
-               clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
                clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
                clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
                break;
 
        case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
-               clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
                clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
                clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
                break;
 
        case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
-               clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
                clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
                clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
                break;