ARM: OMAP5: Clean up iosettings code

[u-boot] / arch / arm / cpu / tegra20-common / warmboot.c

diff --git a/arch/arm/cpu/tegra20-common/warmboot.c b/arch/arm/cpu/tegra20-common/warmboot.c
index 6ce995ef02948fa2a5f4c99a6be5e3c36f324217..0d472cfe33c7f1ae246071f200531117b1b495a7 100644 (file)
--- a/arch/arm/cpu/tegra20-common/warmboot.c
+++ b/arch/arm/cpu/tegra20-common/warmboot.c
@@ -24,17 +24,17 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/errno.h>
-#include <asm/arch/ap20.h>
-#include <asm/arch/clk_rst.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/pmc.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/fuse.h>
 #include <asm/arch/emc.h>
 #include <asm/arch/gp_padctrl.h>
-#include <asm/arch/warmboot.h>
+#include <asm/arch/pinmux.h>
 #include <asm/arch/sdram_param.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/fuse.h>
+#include <asm/arch-tegra/warmboot.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -46,7 +46,7 @@ DECLARE_GLOBAL_DATA_PTR;
  * This is the place in SRAM where the SDRAM parameters are stored. There
  * are 4 blocks, one for each RAM code
  */
-#define SDRAM_PARAMS_BASE      (AP20_BASE_PA_SRAM + 0x188)
+#define SDRAM_PARAMS_BASE      (NV_PA_BASE_SRAM + 0x188)
 
 /* TODO: If we later add support for the Misc GP controller, refactor this */
 union xm2cfga_reg {
@@ -361,8 +361,8 @@ int warmboot_prepare_code(u32 seg_address, u32 seg_length)
        /* Populate the header. */
        dst_header->length_insecure = length + sizeof(struct wb_header);
        dst_header->length_secure = length + sizeof(struct wb_header);
-       dst_header->destination = AP20_WB_RUN_ADDRESS;
-       dst_header->entry_point = AP20_WB_RUN_ADDRESS;
+       dst_header->destination = NV_WB_RUN_ADDRESS;
+       dst_header->entry_point = NV_WB_RUN_ADDRESS;
        dst_header->code_length = length;
 
        if (is_encrypted) {