#include <common.h>
#include <asm/io.h>
#include <asm/errno.h>
-#include <asm/arch/ap20.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
-#include <asm/arch/pmc.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/fuse.h>
#include <asm/arch/emc.h>
#include <asm/arch/gp_padctrl.h>
-#include <asm/arch/warmboot.h>
+#include <asm/arch/pinmux.h>
#include <asm/arch/sdram_param.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/fuse.h>
+#include <asm/arch-tegra/warmboot.h>
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_TEGRA_CLOCK_SCALING
-#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA20_LP0"
+#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA_LP0"
#endif
/*
* This is the place in SRAM where the SDRAM parameters are stored. There
* are 4 blocks, one for each RAM code
*/
-#define SDRAM_PARAMS_BASE (AP20_BASE_PA_SRAM + 0x188)
+#define SDRAM_PARAMS_BASE (NV_PA_BASE_SRAM + 0x188)
/* TODO: If we later add support for the Misc GP controller, refactor this */
union xm2cfga_reg {
u32 ram_code;
struct sdram_params sdram;
struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
struct apb_misc_gp_ctlr *gp =
- (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+ (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
struct emc_ctlr *emc = emc_get_controller(gd->fdt_blob);
union scratch2_reg scratch2;
union scratch4_reg scratch4;
{
u32 major_id;
struct apb_misc_gp_ctlr *gp =
- (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+ (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
major_id = (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >>
HIDREV_MAJORPREV_SHIFT;
static int ap20_is_odm_production_mode(void)
{
- struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE;
+ struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
if (!is_failure_analysis_mode(fuse) &&
is_odm_production_mode_fuse_set(fuse))
static int ap20_is_production_mode(void)
{
- struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE;
+ struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
if (get_major_version() == 0)
return 1;
{
u32 chip_id;
struct apb_misc_gp_ctlr *gp =
- (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+ (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >>
HIDREV_CHIPID_SHIFT;
/* Populate the header. */
dst_header->length_insecure = length + sizeof(struct wb_header);
dst_header->length_secure = length + sizeof(struct wb_header);
- dst_header->destination = AP20_WB_RUN_ADDRESS;
- dst_header->entry_point = AP20_WB_RUN_ADDRESS;
+ dst_header->destination = NV_WB_RUN_ADDRESS;
+ dst_header->entry_point = NV_WB_RUN_ADDRESS;
dst_header->code_length = length;
if (is_encrypted) {