arm: dts: imx6ul-isiot: Add I2C nodes

[u-boot] / arch / arm / dts / armada-8040-db.dts

diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts
index 86666a128c1ef1786c89d7fdc891c1fbf2afa81d..40def9d6cddff4551c1ded6b13c08fbfe241b382 100644 (file)
--- a/arch/arm/dts/armada-8040-db.dts
+++ b/arch/arm/dts/armada-8040-db.dts
@@ -71,6 +71,41 @@
        status = "okay";
 };
 
+&ap_pinctl {
+       /* MPP Bus:
+        * SDIO  [0-10]
+        * UART0 [11,19]
+        */
+                 /* 0 1 2 3 4 5 6 7 8 9 */
+       pin-func = < 1 1 1 1 1 1 1 1 1 1
+                    1 3 0 0 0 0 0 0 0 3 >;
+};
+
+&cpm_pinctl {
+       /* MPP Bus:
+        * [0-31] = 0xff: Keep default CP0_shared_pins:
+        * [11] CLKOUT_MPP_11 (out)
+        * [23] LINK_RD_IN_CP2CP (in)
+        * [25] CLKOUT_MPP_25 (out)
+        * [29] AVS_FB_IN_CP2CP (in)
+        * [32,34] SMI
+        * [31]    GPIO: push button/Wake
+        * [35-36] GPIO
+        * [37-38] I2C
+        * [40-41] SATA[0/1]_PRESENT_ACTIVEn
+        * [42-43] XSMI
+        * [44-55] RGMII1
+        * [56-62] SD
+        */
+               /*   0    1    2    3    4    5    6    7    8    9 */
+       pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+                    0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+                    0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+                    0xff 0    7    0    7    0    0    2    2    0
+                    0    0    8    8    1    1    1    1    1    1
+                    1    1    1    1    1    1    0xe  0xe  0xe  0xe
+                    0xe  0xe  0xe >;
+};
 
 /* CON5 on CP0 expansion */
 &cpm_pcie2 {
@@ -78,6 +113,8 @@
 };
 
 &cpm_i2c0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&cpm_i2c0_pins>;
        status = "okay";
        clock-frequency = <100000>;
 };
@@ -97,12 +134,31 @@
        status = "okay";
 };
 
+&cps_pinctl {
+       /* MPP Bus:
+        * [0-11]  RGMII0
+        * [13-16] SPI1
+        * [27,31] GE_MDIO/MDC
+        * [32-62] = 0xff: Keep default CP1_shared_pins:
+        */
+               /*   0    1    2    3    4    5    6    7    8    9 */
+       pin-func = < 0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3
+                    0x3  0x3  0xff 0x3  0x3  0x3  0x3  0xff 0xff 0xff
+                    0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8  0xff 0xff
+                    0xff 0x8  0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+                    0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+                    0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+                    0xff 0xff 0xff >;
+};
+
 /* CON5 on CP1 expansion */
 &cps_pcie2 {
        status = "okay";
 };
 
 &cps_spi1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&cps_spi1_pins>;
        status = "okay";
 
        spi-flash@0 {