arm: freescale: Rename initdram() to fsl_initdram()

[u-boot] / arch / arm / dts / armada-8040-db.dts

diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts
index 6e6f182fb2971a895efded70f6e4ae7b7287bd39..f1f196f563a110d77a8ce97be1ed8629726f4211 100644 (file)
--- a/arch/arm/dts/armada-8040-db.dts
+++ b/arch/arm/dts/armada-8040-db.dts
@@ -55,18 +55,110 @@
                stdout-path = "serial0:115200n8";
        };
 
+       aliases {
+               i2c0 = &cpm_i2c0;
+               spi0 = &cps_spi1;
+       };
+
        memory@00000000 {
                device_type = "memory";
                reg = <0x0 0x0 0x0 0x80000000>;
        };
 };
 
-&i2c0 {
+/* Accessible over the mini-USB CON9 connector on the main board */
+&uart0 {
+       status = "okay";
+};
+
+&ap_pinctl {
+       /* MPP Bus:
+        * SDIO  [0-10]
+        * UART0 [11,19]
+        */
+                 /* 0 1 2 3 4 5 6 7 8 9 */
+       pin-func = < 1 1 1 1 1 1 1 1 1 1
+                    1 3 0 0 0 0 0 0 0 3 >;
+};
+
+&cpm_pinctl {
+       /* MPP Bus:
+        * [0-31] = 0xff: Keep default CP0_shared_pins:
+        * [11] CLKOUT_MPP_11 (out)
+        * [23] LINK_RD_IN_CP2CP (in)
+        * [25] CLKOUT_MPP_25 (out)
+        * [29] AVS_FB_IN_CP2CP (in)
+        * [32,34] SMI
+        * [31]    GPIO: push button/Wake
+        * [35-36] GPIO
+        * [37-38] I2C
+        * [40-41] SATA[0/1]_PRESENT_ACTIVEn
+        * [42-43] XSMI
+        * [44-55] RGMII1
+        * [56-62] SD
+        */
+               /*   0    1    2    3    4    5    6    7    8    9 */
+       pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+                    0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+                    0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+                    0xff 0    7    0    7    0    0    2    2    0
+                    0    0    8    8    1    1    1    1    1    1
+                    1    1    1    1    1    1    0xe  0xe  0xe  0xe
+                    0xe  0xe  0xe >;
+};
+
+/* CON5 on CP0 expansion */
+&cpm_pcie2 {
+       status = "okay";
+};
+
+&cpm_i2c0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&cpm_i2c0_pins>;
        status = "okay";
        clock-frequency = <100000>;
 };
 
-&spi0 {
+/* CON4 on CP0 expansion */
+&cpm_sata0 {
+       status = "okay";
+};
+
+/* CON9 on CP0 expansion */
+&cpm_usb3_0 {
+       status = "okay";
+};
+
+/* CON10 on CP0 expansion */
+&cpm_usb3_1 {
+       status = "okay";
+};
+
+&cps_pinctl {
+       /* MPP Bus:
+        * [0-11]  RGMII0
+        * [13-16] SPI1
+        * [27,31] GE_MDIO/MDC
+        * [32-62] = 0xff: Keep default CP1_shared_pins:
+        */
+               /*   0    1    2    3    4    5    6    7    8    9 */
+       pin-func = < 0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3
+                    0x3  0x3  0xff 0x3  0x3  0x3  0x3  0xff 0xff 0xff
+                    0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8  0xff 0xff
+                    0xff 0x8  0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+                    0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+                    0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+                    0xff 0xff 0xff >;
+};
+
+/* CON5 on CP1 expansion */
+&cps_pcie2 {
+       status = "okay";
+};
+
+&cps_spi1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&cps_spi1_pins>;
        status = "okay";
 
        spi-flash@0 {
@@ -93,58 +185,117 @@
        };
 };
 
-/* Accessible over the mini-USB CON9 connector on the main board */
-&uart0 {
+/* CON4 on CP1 expansion */
+&cps_sata0 {
        status = "okay";
 };
 
-
-/* CON5 on CP0 expansion */
-&cpm_pcie2 {
+/* CON9 on CP1 expansion */
+&cps_usb3_0 {
        status = "okay";
 };
 
-&cpm_i2c0 {
+/* CON10 on CP1 expansion */
+&cps_usb3_1 {
        status = "okay";
-       clock-frequency = <100000>;
 };
 
-/* CON4 on CP0 expansion */
-&cpm_sata0 {
-       status = "okay";
+&cpm_comphy {
+       /*
+        * Serdes Configuration:
+        * Lane 0: SGMII2
+        * Lane 1: USB3_HOST0
+        * Lane 2: KR (10G)
+        * Lane 3: SATA1
+        * Lane 4: USB3_HOST1
+        * Lane 5: PEX2x1
+        */
+       phy0 {
+               phy-type = <PHY_TYPE_SGMII2>;
+               phy-speed = <PHY_SPEED_3_125G>;
+       };
+
+       phy1 {
+               phy-type = <PHY_TYPE_USB3_HOST0>;
+       };
+
+       phy2 {
+               phy-type = <PHY_TYPE_KR>;
+       };
+
+       phy3 {
+               phy-type = <PHY_TYPE_SATA1>;
+       };
+
+       phy4 {
+               phy-type = <PHY_TYPE_USB3_HOST1>;
+       };
+
+       phy5 {
+               phy-type = <PHY_TYPE_PEX2>;
+       };
 };
 
-/* CON9 on CP0 expansion */
-&cpm_usb3_0 {
-       status = "okay";
+&cps_comphy {
+       /*
+        * Serdes Configuration:
+        * Lane 0: SGMII2
+        * Lane 1: USB3_HOST0
+        * Lane 2: KR (10G)
+        * Lane 3: SATA1
+        * Lane 4: Unconnected
+        * Lane 5: PEX2x1
+        */
+       phy0 {
+               phy-type = <PHY_TYPE_SGMII2>;
+               phy-speed = <PHY_SPEED_3_125G>;
+       };
+
+       phy1 {
+               phy-type = <PHY_TYPE_USB3_HOST0>;
+       };
+
+       phy2 {
+               phy-type = <PHY_TYPE_KR>;
+       };
+
+       phy3 {
+               phy-type = <PHY_TYPE_SATA1>;
+       };
+
+       phy4 {
+               phy-type = <PHY_TYPE_UNCONNECTED>;
+       };
+
+       phy5 {
+               phy-type = <PHY_TYPE_PEX2>;
+       };
 };
 
-/* CON10 on CP0 expansion */
-&cpm_usb3_1 {
+&cpm_utmi0 {
        status = "okay";
 };
 
-/* CON5 on CP1 expansion */
-&cps_pcie2 {
+&cpm_utmi1 {
        status = "okay";
 };
 
-&cps_i2c0 {
+&cps_utmi0 {
        status = "okay";
-       clock-frequency = <100000>;
 };
 
-/* CON4 on CP1 expansion */
-&cps_sata0 {
-       status = "okay";
+&cpm_mdio {
+       phy1: ethernet-phy@1 {
+               reg = <1>;
+       };
 };
 
-/* CON9 on CP1 expansion */
-&cps_usb3_0 {
+&cpm_ethernet {
        status = "okay";
 };
 
-/* CON10 on CP1 expansion */
-&cps_usb3_1 {
+&cpm_eth2 {
        status = "okay";
+       phy = <&phy1>;
+       phy-mode = "rgmii-id";
 };